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Name Bernd Becker, Prof. Dr. Bernd Becker,  Prof. Dr.
Adresse Technische Fakultät
Albert-Ludwigs-Universität
Georges Köhler Allee, Gebäude 51
79110 Freiburg im Breisgau
Deutschland
Büro Gebäude 51, Raum 01..007
Telefon ++49 +761 203-8141
Fax ++49 +761 203-8142
eMail becker@informatik.uni-freiburg.de
PGP-Key Public-Key
fingerprint = 4896 9355 CC38 B6C7 8BB6 9CD0 7F03 2F69 506C 3DC7
Website http://ira.informatik.uni-freiburg.de/~becker/home.html

Bernd Becker

Jahre: 2016 | 2015 | 2014 | 2013 | 2012 | 2011 | 2010 | 2009 | 2008 | 2007 | 2006 | 2005 | 2004 | 2003 | 2002 | 2001 | 2000 | 1999 | 1998 | 1997 | 1996 | 1995 | 1994 | 1993 | 1992 | 1991 | 1988 | 1987 | 1986 | 1983

    2016

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    • Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian
      On Optimal Power-aware Path Sensitization
      2016 2016 25nd IEEE Asian Test Symposium (ATS)
    • Mathias Soeken, Pascal Raiola, Baruch Sterin, Bernd Becker, Giovanni De Micheli, Matthias Sauer
      SAT-based Combinational and Sequential Dependency Computation
      2016 Haifa Verification Conference (HVC)
    • Jan Burchard, Tobias Schubert, Bernd Becker
      Distributed Parallel #SAT Solving
      2016 IEEE Cluster 2016
    • Michael Kochte, Rafal Baranowski, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich
      Formal Verification of Secure Reconfigurable Scan Network Infrastructure
      2016 IEEE European Test Symposium
    • Michael Kochte, Matthias Sauer, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
      SHIVA: Sichere Hardware in der Informationsverarbeitung Formaler Nachweis komplexer Sicherheitseigenschaften in rekonfigurierbarer Infrastruktur
      2016 eda Workshop
    • Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
      Effective Generation and Evaluation of Diagnostic SBST Programs
      2016 IEEE VLSI Test Symposium
    • Linus Feiten, Matthias Sauer, Bernd Becker
      On Metrics to Quantify the Inter-Device Uniqueness of PUFs
      2016 TRUDEVICE Workshop, Dresden
    • Matthias Sauer, Sven Reimer, Daniel Tille, Karsten Scheibler, Dominik Erb, Ulrike Pfannkuchen, Bernd Becker
      Clock Cycle Aware Encoding for SAT-based Circuit Initialization
      2016 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Karsten Scheibler, Dominik Erb, Bernd Becker
      Accurate CEGAR-based ATPG in Presence of Unknown Values for Large Industrial Designs
      2016 Conf. on Design, Automation and Test in Europe
    • Felix Neubauer, Karsten Scheibler, Bernd Becker, Ahmed Mahdi, Martin Fränzle, Tino Teige, Tom Bienmüller, Detlef Fehrer
      Accurate Dead Code Detection in Embedded C Code by Arithmetic Constraint Solving
      2016 First International Workshop on Satisfiability Checking and Symbolic Computation - FETOPEN-CSA SC2 Workshop - Affiliated with SYNASC 2016
    • Karsten Scheibler, Felix Neubauer, Ahmed Mahdi, Martin Fränzle, Tino Teige, Tom Bienmüller, Detlef Fehrer, Bernd Becker
      Accurate ICP-based Floating-Point Reasoning
      2016 Formal Methods in Computer-Aided Design
    • Ahmed Mahdi, Karsten Scheibler, Felix Neubauer, Martin Fränzle, Bernd Becker
      Advancing software model checking beyond linear arithmetic theories
      2016 Twelfth Haifa Verification Conference 2016
    • Karsten Scheibler, Dominik Erb, Bernd Becker
      Applying Tailored Formal Methods to X-ATPG
      2016 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”
    • Thomas Metz, Uwe Wagschal, Thomas Waldvogel, Marko Bachl, Linus Feiten, Bernd Becker
      Das Debat-O-Meter: ein neues Instrument zur Analyse von TV-Duellen
      2016 ZSE Zeitschrift für Staats- und Europawissenschaften, Band: 14, Nummer: 1, Seiten: 124 - 149
    • Ralf Wimmer, Christoph Scholl, Karina Wimmer, Bernd Becker
      Dependency Schemes for DQBF
      2016 Proceedings of the 19th International Conference on Theory and Applications of Satisfiability Testing (SAT), Springer, Band: 9710, Seiten: 473 - 489
    • Karsten Scheibler, Felix Neubauer, Ahmed Mahdi, Martin Fränzle, Tino Teige, Tom Bienmüller, Detlef Fehrer, Bernd Becker
      Extending iSAT3 with ICP-Contractors for Bitwise Integer Operations
      AVACS Technical Report, SFB/TR 14 AVACS, Subproject T1, Band: 116, 2016
    • Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
      Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns
      2016 to be published at the 21st Asia and South Pacific Design Automation Conference
    • Linus Feiten, Sebastian Sester, Christian Zimmermann, Sebastian Volkmann, Laura Wehle, Bernd Becker
      Revocable Anonymisation in Video Surveillance: A "Digital Cloak of Invisibility"
      In: Technology and Intimacy: Choice or Coercion
      2016, Springer International Publishing, Seiten: 314 - 327, ISBN: 978-3-319-44804-6
    • Bernd Becker, Katrin Weber, Linus Feiten
      SMartphones In der LEhre (SMILE)
      In: Kreativ, Innovativ, Motivierend - Lehrkonzepte in der Praxis: Der Instructional Development Award (IDA) der Universität Freiburg
      2016, Universitäts Verlag Webler (UVW), Seiten: 117 - 133, ISBN: 978-3-946017-01-1
    • Karina Wimmer, Ralf Wimmer, Christoph Scholl, Bernd Becker
      Skolem Functions for DQBF
      2016 Proceedings of the 14th International Symposium on Automated Technology for Verification and Analysis (ATVA), Springer
    • Karina Wimmer, Ralf Wimmer, Christoph Scholl, Bernd Becker
      Skolem Functions for DQBF (Extended Version)
      , 2016
    • Jan Burchard, Maël Gay, Jan Horáček, Ange-Salomé Messeng Ekossono, Tobias Schubert, Bernd Becker, Ilia Polian, Martin Kreuzer
      Small Scale AES Toolbox: Algebraic and Propositional Formulas, Circuit-Implementations and Fault Equations
      2016 FCTRU'16
    • Linus Feiten, Jonathan Oesterle, Tobias Martin, Matthias Sauer, Bernd Becker
      Systemic Frequency Biases in Ring Oscillator PUFs on FPGAs
      2016 IEEE Transactions on Multi-Scale Computing Systems (TMSCS), Band: PP, Nummer: 99
    • Matthias Sauer, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian
      Utilizing Intrinsic Delay Variability in Complex Digital Circuits for Defining PUF Behavior
      2016 TRUDEVICE Workshop, Dresden

    2015

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    • Jan Burchard, Tobias Schubert, Bernd Becker
      Laissez-Faire Caching for Parallel #SAT Solving
      2015 International Conference on Theory and Applications of Satisfiability Testing, Band: 9340, Seiten: 46 - 61
    • Linus Feiten, Tobias Martin, Matthias Sauer, Bernd Becker
      Improving RO-PUF Quality on FPGAs by Incorporating Design-Dependent Frequency Biases
      2015 IEEE European Test Symposium
    • Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
      Identification of High Power Consuming Areas with Gate Type and Logic Level Information
      2015 IEEE European Test Symposium
    • Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
      On the Automatic Generation of SBST Test Programs for In-Field Test
      2015 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Bettina Braitling, Luis María Ferrer Fioriti, Hassan Hatefi, Ralf Wimmer, Bernd Becker, Holger Hermanns
      Abstraction-based Computation of Reward Measures for Markov Automata
      2015 Mumbai, India Int'l Conf. Verification, Model Checking, and Abstract Interpretation (VMCAI), Band: 8931, Seiten: 172 - 189
    • Dominik Erb, Michael A. Kochte, Sven Reimer, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
      Accurate QBF-based Test Pattern Generation in Presence of Unknown Values
      2015 Computer-Aided Design of Integrated Circuits and Systems (TCAD)
    • Linus Feiten, Tobias Martin, Matthias Sauer, Bernd Becker
      Analysis and utilisation of deviations in RO-PUFs under altered FPGA designs
      2015 TRUDEVICE Workshop, Grenoble
    • Hassan Hatefi, Bettina Braitling, Ralf Wimmer, Luis Maria Ferrer Fioriti, Holger Hermanns, Bernd Becker
      Cost vs. Time in Stochastic Games and Markov Automata
      2015 International Symposium on Dependable Software Engineering: Theory, Tools and Applications (SETTA) Proc. of SETTA, Springer-Verlag, Band: 9409, Seiten: 19 - 34
    • Linus Feiten, Matthias Sauer, Tobias Schubert, Victor Tomashevich, Ilia Polian, Bernd Becker
      Formal Vulnerability Analysis of Security Components
      2015 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Band: 34, Nummer: 8, Seiten: 1358 - 1369
    • Andreas Riefert, Matthias Sauer, Sudhakar Reddy, Bernd Becker
      Improving Diagnosis Resolution of a Fault Detection Test Set
      2015 VLSI Test Symposium
    • Karsten Scheibler, Dominik Erb, Bernd Becker
      Improving Test Pattern Generation in Presence of Unknown Values beyond Restricted Symbolic Logic
      2015 to be published at European Test Symposium (ETS)
    • Bernd Becker, Matthias Sauer, Christoph Scholl, Ralf Wimmer
      Modeling Unknown Values in Test and Verification
      In: Formal Modeling and Verification of Cyber-Physical Systems (Proceedings of the 1st International Summer School on Methods and Tools for the Design of Digital Systems)
      2015, Springer, Rolf Drechsler, Ulrich Kühne, Seiten: 122 - 150, Rolf Drechsler, Ulrich Kühne, ISBN: 978-3-658-09993-0
    • Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
      Multi-Cycle Circuit Parameter Independent ATPG for Interconnect Open Defects
      2015 33rd VLSI Test Symposium (VTS)
    • Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
      On the Automatic Generation of SBST Test Programs for In-Field Test
      2015 Conf. on Design, Automation and Test in Europe
    • Matthias Sauer, Bernd Becker, Ilia Polian
      PHAETON: A SAT-based Framework for Timing-aware Path Sensitization
      2015 Ieee T Comput, Band: PP, Nummer: 99
    • Ralf Wimmer, Karina Gitina, Jennifer Nist, Christoph Scholl, Bernd Becker
      Preprocessing for DQBF
      2015 Proceedings of the 18th International Conference on Theory and Applications of Satisfiability Testing (SAT), Springer, Band: 9340, Seiten: 173 - 190
    • Karina Gitina, Ralf Wimmer, Sven Reimer, Matthias Sauer, Christoph Scholl, Bernd Becker
      Solving DQBF Through Quantifier Elimination
      2015 Conf. on Design, Automation and Test in Europe
    • Karsten Scheibler, Leonore Winterer, Ralf Wimmer, Bernd Becker
      Towards Verification of Artificial Neural Networks
      2015 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”
    • Ernst Moritz Hahn, Holger Hermanns, Ralf Wimmer, Bernd Becker
      Transient Reward Approximation for Continuous-Time Markov Chains
      2015 Ieee T Reliab, Band: 64, Nummer: 4
    • Christian Miller, Paolo Marin, Bernd Becker
      Verification of Partial Designs Using Incremental QBF
      2015 Ai Commun, Band: 28, Nummer: 2, Seiten: 283 - 307

    2014

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    • Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
      Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects
      2014 23nd IEEE Asian Test Symposium (ATS)
    • Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker
      Incremental Encoding and Solving of Cardinality Constraints
      2014 International Symposium on Automated Technology for Verification and Analysis, Springer International Publishing, Band: 8837, Seiten: 297 - 313
    • Sven Reimer, Matthias Sauer, Paolo Marin, Bernd Becker
      QBF with Soft Variables
      2014 International Workshop on Automated Verification of Critical Systems (AVOCS)
    • Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer
      Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization
      2014 International Conference on Design Technology of Integrated Systems In Nanoscale Era (DTIS)
    • Matthias Sauer, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker
      Variation-Aware Deterministic ATPG
      2014 IEEE European Test Symposium , Seiten: 1 - 6
    • Matthias Sauer, Sven Reimer, Sudhakar M. Reddy, Bernd Becker
      Efficient SAT-based Circuit Initialization for Large Designs
      2014 Int'l Conf. on VLSI Design
    • Nils Jansen, Florian Corzilius, Matthias Volk, Ralf Wimmer, Erika Ábrahám, Joost-Pieter Katoen, Bernd Becker
      Accelerating Parametric Probabilistic Verification
      2014 Int'l Conf. on Quantitative Evaluation of Systems (QEST), Springer-Verlag, Band: 8657, Seite: 404-420
    • Tobias Schubert, Marc Pfeifer, Bernd Becker
      Accurate Controlling of Velocity on a Mobile Robot
      2014 29th International Conference on Computers and Their Applications
    • Andreas Riefert, Lyl Ciganda, Matthias Sauer, Paolo Bernadi, Matteo Sonza Reorda, Bernd Becker
      An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults
      2014 Conf. on Design, Automation and Test in Europe
    • Sreedhar Saseendran Kumar, Jan Wülfing, Joschka Boedecker, Ralf Wimmer, Martin Riedmiller, Bernd Becker, Ulrich Egert
      Autonomous Control of Network Activity
      2014 9th International Meeting on Substrate-Integrated Microelectrode Arrays (MEA)
    • Erika Ábrahám, Bernd Becker, Christian Dehnert, Nils Jansen, Joost-Pieter Katoen, Ralf Wimmer
      Counterexample Generation for Discrete-Time Markov Models: An Introductory Survey
      In: International School on Formal Methods for the Design of Computer, Communication, and Software Systems (SFM), Advanced Lectures
      2014, Springer-Verlag, Seiten: 65 - 121,
    • Dominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker
      Efficient SMT-based ATPG for Interconnect Open Defects
      2014 Conf. on Design, Automation and Test in Europe
    • Dominik Erb, Michael Koche, Matthias Sauer, Stefan Hillebrecht, Tobias Schubert, Hans-Joachim Wunderlich, Bernd Becker
      Exact Logic and Fault Simulation in Presence of Unknowns
      2014 ACM Transactions on Design Automation of Electronic Systems (TODAES), Band: 19, Seiten: 28:1 - 28:17
    • Linus Feiten, Andreas Spilla, Matthias Sauer, Tobias Schubert, Bernd Becker
      Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs
      2014 Information Security Journal: A Global Perspective, Band: 22, Nummer: 5-6, Seiten: 265 - 273
    • Karsten Scheibler, Bernd Becker
      Implication Graph Compression inside the SMT Solver iSAT3
      2014 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”
    • Bettina Braitling, Luis María Ferrer Fioriti, Hassan Hatefi, Ralf Wimmer, Bernd Becker, Holger Hermanns
      MeGARA: Menu-based Game Abstraction and Abstraction Refinement of Markov Automata
      2014 International Workshop on Quantitative Aspects of Programming Languages and Systems , Band: EPTCS
    • Ralf Wimmer, Nils Jansen, Erika Ábrahám, Joost-Pieter Katoen, Bernd Becker
      Minimal Counterexamples for Linear-Time Probabilistic Verification
      2014 Theor Comput Sci
    • Nils Jansen, Ralf Wimmer, Erika Ábrahám, Barna Zajzon, Joost-Pieter Katoen, Bernd Becker, Johann Schuster
      Symbolic Counterexample Generation for Large Discrete-Time Markov Chains
      2014 Sci Comput Program, Band: 91, Nummer: A, Seiten: 90 - 114
    • Dominik Erb, Karsten Scheibler, Michael Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
      Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic
      2014 Int'l Test Conf.
    • Karsten Scheibler, Bernd Becker
      Using Interval Constraint Propagation for Pseudo-Boolean Constraint Solving
      2014 Formal Methods in Computer-Aided Design
    • Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker
      Using MaxBMC for Pareto-Optimal Circuit Initialization
      2014 Conf. on Design, Automation and Test in Europe

    2013

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    • Linus Feiten, Katrin Weber, Bernd Becker
      SMILE: Smartphones in der Lehre – ein Rück- und Überblick
      2013 INFORMATIK 2013 Gesellschaft für Informatik (GI), Matthias Horbach, Band: P-220, Seiten: 255 - 269
    • Tobias Schubert, Jan Burchard, Matthias Sauer, Bernd Becker
      S-Trike: A Mobile Robot Platform for Higher Education
      2013 International Conference on Computer Applications in Industry and Engineering, Seiten: 243 - 248
    • Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Victor Tomashevich, Eberhard Böhl, Ilia Polian, Bernd Becker
      #SAT for Vulnerability Analysis of Security Components
      2013 (Workshop-Paper, Informal Proceedings) IEEE European Test Symposium
    • Ulrich Loup, Karsten Scheibler, Florian Corzilius, Erika Ábrahám, Bernd Becker
      A Symbiosis of Interval Constraint Propagation and Cylindrical Algebraic Decomposition
      2013 CADE, Springer, Band: 7898, Seiten: 193 - 207
    • Benjamin Andres, Matthias Sauer, Martin Gebser, Tobias Schubert, Bernd Becker, Torsten Schaub
      Accurate Computation of Sensitizable Paths using Answer Set Programming
      2013 Int. Conf. on Logic Programming and Nonmonotonic Reasoning, Seiten: 92 - 101
    • Dominik Erb, Michael A Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
      Accurate Multi-Cycle ATPG in Presence of X-Values
      2013 22nd IEEE Asian Test Symposium (ATS)
    • Stefan Hillebrecht, Michael A. Kochte, Dominik Erb, Hans-Joachim Wunderlich, Bernd Becker
      Accurate QBF-based test pattern generation in presence of unknown values
      2013 Conf. on Design, Automation and Test in Europe
    • Linus Feiten, Andreas Spilla, Matthias Sauer, Tobias Schubert, Bernd Becker
      Analysis of Ring Oscillator PUFs on 60nm FPGAs
      2013 TRUDEVICE Workshop, Avignon
    • Matthias Sauer, Sven Reimer, Stefan Kupferschmid, Tobias Schubert, Paolo Marin, Bernd Becker
      Applying BMC, Craig Interpolation and MAX-SAT to Functional Justification in Sequential Circuits
      2013 RCRA International Workshop on Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion
    • Karsten Scheibler, Matthias Sauer, Kohei Miyase, Bernd Becker
      Controlling Small-Delay Test Power Consumption using Satisfibility Modulo Theory Solving
      2013 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Matthias Sauer, Bernd Becker, Subhasish Mitra
      Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics
      2013 Custom Integrated Circuits Conference, Seiten: 1 - 4
    • Matthias Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung-Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra, Bernd Becker
      Early-Life-Failure Detection using SAT-based ATPG
      2013 Int'l Test Conf., Seiten: 1 - 10
    • Matthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker
      Efficient SAT-Based Dynamic Compaction and Relaxation for Longest Sensitizable Paths
      2013 Conf. on Design, Automation and Test in Europe, Seiten: 448 - 453
    • Karina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker
      Equivalence Checking for Partial Implementations Revisited
      2013 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Universität Rostock ITMZ, Seiten: 61 - 70
    • Karina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker
      Equivalence Checking of Partial Designs using Dependency Quantified Boolean Formulae
      2013 Int'l Conf. on Computer Design, IEEE Computer Society, Seiten: 396 - 403
    • Katrin Weber, Bernd Becker
      Formative Evaluation des mobilen Classroom-Response-Systems SMILE
      2013 GMW 2013 eLearing, Seiten: 277 - 289
    • Ralf Wimmer, Nils Jansen, Andreas Vorpahl, Erika Ábrahám, Joost-Pieter Katoen, Bernd Becker
      High-Level Counterexamples for Probabilistic Automata
      2013 Springer-Verlag, Band: 8054, Seiten: 18 - 33
    • Ralf Wimmer, Nils Jansen, Andreas Vorpahl, Erika Ábrahám, Joost-Pieter Katoen, Bernd Becker
      High-Level Counterexamples for Probabilistic Automata
      , Band: arxiv:1305.5055, 2013
    • Andreas Riefert, Joerg Mueller, Matthias Sauer, Wolfram Burgard, Bernd Becker
      Identification of Critical Variables using an FPGA-based Fault Injection Framework
      2013 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Andreas Riefert, Joerg Mueller, Matthias Sauer, Wolfram Burgard, Bernd Becker
      Identification of Critical Variables using an FPGA-based Fault Injection Framework
      2013 VLSI Test Symp., Seiten: 1 - 6
    • Matthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker
      Provably Optimal Test Cube Generation Using Quantified Boolean Formula Solving
      2013 ASP Design Automation Conf.
    • Karsten Scheibler, Stefan Kupferschmid, Bernd Becker
      Recent Improvements in the SMT Solver iSAT
      2013 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”
    • Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker
      SAT-based Analysis of Sensitisable Paths
      2013 IEEE Design & Test of Computers, Band: 30, Nummer: 4, Seiten: 81 - 88
    • Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
      Search Space Reduction for Low-Power Test Generation
      2013 22nd IEEE Asian Test Symposium (ATS)
    • Bettina Braitling, Ralf Wimmer, Bernd Becker, Erika Ábrahám
      Stochastic Bounded Model Checking: Bounded Rewards and Compositionality
      2013 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Seiten: 243 - 254
    • Matthias Sauer, Jan Burchard, Tobias Schubert, Ilia Polian, Bernd Becker
      Waveform-Guided Fault Injection by Clock Manipulation
      2013 TRUDEVICE Workshop

    2012

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    • Alexander Czutro, Michael Imhof, Jie Jiang, Abdullah Mumtaz, Matthias Sauer, Bernd Becker, Ilia Polian, Hans-Joachim Wunderlich
      Variation-Aware Fault Grading
      2012 IEEE Asian Test Symp., Seiten: 344 - 349
    • Christian Miller, Paolo Marin, Bernd Becker
      A Dynamic QBF Preprocessing Approach for the Verification of Incomplete Designs
      2012 Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion, Band: 19
    • Sven Reimer, Florian Pigorsch, Christoph Scholl, Bernd Becker
      Enhanced Integration of QBF Solving Techniques
      2012 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Seiten: 133 - 143
    • Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Eberhard Böhl, Ilia Polian, Bernd Becker
      #SAT-Based Vulnerability Analysis of Security Components -- A Case Study
      2012 IEEE International Symposium on Defect and Fault Tolerance (DFT), Seiten: 49 - 54
    • Bernd Becker, Ruediger Ehlers, Matthew Lewis, Paolo Marin
      ALLQBF Solving by Computational Learning
      2012 Automated Technology for Verification and Analysis, Springer, Band: 7561, Seiten: 370 - 384
    • Benjamin Andres, Matthias Sauer, Martin Gebser, Tobias Schubert, Bernd Becker, Torsten Schaub
      Accurate Computation of Longest Sensitizable Paths using Answer Set Programming
      2012 GMM/ITG-Fachtagung “Zuverlässigkeit und Entwurf”
    • Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Sudhakar M. Reddy, Bernd Becker
      Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation
      2012 Int'l Conf. on VLSI Design
    • Stefan Hillebrecht, Michael Kochte, Hans-Joachim Wunderlich, Bernd Becker
      Exact Stuck-at Fault Classification in Presence of Unknowns
      2012 IEEE European Test Symp.
    • Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
      Functional Justification in Sequential Circuits using SAT and Craig Interpolation
      2012 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
      Functional Test of Small-Delay Faults using SAT and Craig Interpolation
      2012 Int'l Test Conf., Seiten: 1 - 8
    • Paolo Marin, Christian Miller, Bernd Becker
      Incremental QBF Preprocessing for Partial Design Verification - (Poster Presentation)
      2012 Int'l Conf. on Theory and Applications of Satisfiability Testing, Springer, Band: 7317, Seiten: 473 - 474
    • Ralf Wimmer, Nils Jansen, Erika Ábrahám, Joost-Pieter Katoen, Bernd Becker
      Minimal Counterexamples for Refuting omega-Regular Properties of Markov Decision Processes
      AVACS Technical Report, Nummer: 88, 2012
    • Ralf Wimmer, Bernd Becker, Nils Jansen, Erika Ábrahám, Joost-Pieter Katoen
      Minimal Critical Subsystems as Counterexamples for omega-Regular DTMC Properties
      2012 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Verlag Dr. Kovac, Seiten: 169 - 180
    • Ralf Wimmer, Bernd Becker, Nils Jansen, Erika Ábrahám, Joost-Pieter Katoen
      Minimal Critical Subsystems for Discrete-Time Markov Models
      2012 Int'l Conf. on Tools and Algorithms for the Construction and Analysis of Systems, Springer-Verlag, Band: 7214, Seiten: 299 - 314
    • Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker
      Multi-Conditional ATPG using SAT with Preferences
      2012 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker
      Multi-Conditional SAT-ATPG for Power-Droop Testing
      2012 IEEE European Test Symp.
    • Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
      On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints
      2012 Conf. on Design, Automation and Test in Europe, Seiten: 418 - 423
    • Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
      On the Quality of Test Vectors for Post-Silicon Characterization
      2012 IEEE European Test Symp.
    • Alexander Czutro, Matthias Sauer, Tobias Schubert, Ilia Polian, Bernd Becker
      SAT-ATPG Using Preferences for Improved Detection of Complex Defect Mechanisms
      2012 VLSI Test Symp.
    • Linus Feiten, Manuel Bührer, Sebastian Sester, Bernd Becker
      SMILE - SMARTPHONES IN LECTURES - Initiating a Smartphone-based Audience Response System as a Student Project
      2012 4th International Conference on Computer Supported Education (CSEDU), Seiten: 288 - 293
    • Celia Kändler, Linus Feiten, Katrin Weber, Michael Wiedmann, Manuel Bührer, Sebastian Sester, Bernd Becker
      SMILE - smartphones in a university learning environment: a classroom response system
      2012 International Conference of the Learning Sciences (ICLS), International Society of the Learning Sciences, Band: 2, Seiten: 515 - 516
    • Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker
      Small-Delay-Fault ATPG with Waveform Accuracy
      2012 Int'l Conf. on CAD, Seiten: 30 - 36
    • Nils Jansen, Erika Ábrahám, Barna Zajzon, Ralf Wimmer, Johann Schuster, Joost-Pieter Katoen, Bernd Becker
      Symbolic Counterexample Generation for Discrete-time Markov Chains
      2012 Int'l Symp. on Formal Aspects of Component Software, Springer-Verlag, Band: 7684, Seiten: 134 - 151
    • Nils Jansen, Erika Ábrahám, Matthias Volk, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker
      The COMICS Tool - Computing Minimal Counterexamples for DTMCs
      2012 Automated Technology for Verification and Analysis, Springer-Verlag, Band: 7561, Seiten: 349 - 353
    • Nils Jansen, Erika Ábrahám, Maik Scheffler, Matthias Volk, Andreas Vorpahl, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker
      The COMICS Tool - Computing Minimal Counterexamples for DTMCs
      , Band: arxiv:1206.0603, 2012
    • Ernst Moritz Hahn, Holger Hermanns, Ralf Wimmer, Bernd Becker
      Transient Reward Approximation for Grids, Crowds, and Viruses
      arXiv, Band: arxiv:1212.1251, 2012
    • Paolo Marin, Christian Miller, Matthew Lewis, Bernd Becker
      Verification of Partial Designs Using Incremental QBF Solving
      2012 Conf. on Design, Automation and Test in Europe, Seiten: 623 - 628

    2011

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    • Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
      On the Optimality of K Longest Path Generation
      2011 Workshop on RTL and High Level Testing
    • Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker
      Estimation of Component Criticality in Early Design Steps
      2011 IEEE Int'l Online Testing Symp., Seiten: 104 - 110
    • Christian Miller, Christoph Scholl, Bernd Becker
      Verifying Incomplete Networks of Timed Automata
      2011 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Band: 14
    • Matthias Sauer, Victor Tomashevich, Jörg Müller, Matthew Lewis, Ilia Polian, Bernd Becker, Wolfram Burgard
      An FPGA-Based Framework for Run-time Injection and Analysis of Soft Errors in Microprocessors
      2011 IEEE Int'l Online Testing Symp., Seiten: 182 - 185
    • Pepijn Crouzen, Ernst Moritz Hahn, Holger Hermanns, Abhishek Dhama, Oliver Theel, Ralf Wimmer, Bettina Braitling, Bernd Becker
      Bounded Fairness for Probabilistic Distributed Algorithms
      2011 Int'l Conf. on Application of Concurrency to System Design, IEEE Computer Society, Seiten: 89 - 97
    • Christian Miller, Karina Gitina, Bernd Becker
      Bounded Model Checking of Incomplete Real-time Systems Using Quantified SMT Formulas
      2011 Int'l Workshop on Microprocessor Test and Verification, Seiten: 22 - 27
    • Bettina Braitling, Ralf Wimmer, Bernd Becker, Nils Jansen, Erika Ábrahám
      Counterexample Generation for Markov Chains using SMT-based Bounded Model Checking
      2011 IFIP Int'l Conf. on Formal Methods for Open Object-based Distributed Systems, Springer-Verlag, Band: 6722, Seiten: 75 - 89
    • Stefan Kupferschmid, Bernd Becker
      Craig interpolation in the presence of non-linear constraints
      2011 Formal Modeling and Analysis of Timed Systems, Springer, Seiten: 240 - 255
    • Stefan Kupferschmid, Bernd Becker
      Craigsche Interpolation für Boolesche Kombinationen linearer und nichtlinearer Ungleichungen
      2011 OFFIS-Institut für Informatik, Seiten: 279 - 288
    • Matthias Sauer, Jie Jiang, Alexander Czutro, Ilia Polian, Bernd Becker
      Efficient SAT-Based Search for Longest Sensitisable Paths
      2011 Test Symposium (ATS), 2011 20th Asian, Seiten: 108 - 113
    • Nils Jansen, Erika Ábrahám, Jens Katelaan, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker
      Hierarchical Counterexamples for Discrete-Time Markov Chains
      2011 Int'l Symp. on Automated Technology for Verification and Analysis, Springer-Verlag, Band: 6996, Seiten: 443 - 452
    • Nils Jansen, Erika Ábrahám, Jens Katelaan, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker
      Hierarchical Counterexamples for Discrete-Time Markov Chains
      , Band: AIB-2011-11, 2011
    • Stefan Kupferschmid, Matthew Lewis, Tobias Schubert, Bernd Becker
      Incremental preprocessing methods for use in BMC
      2011 Formal Methods in System Design, Band: 39, Seiten: 185 - 204
    • Sven Reimer, Florian Pigorsch, Christoph Scholl, Bernd Becker
      Integration of Orthogonal QBF Solving Techniques
      2011 Conf. on Design, Automation and Test in Europe, Seiten: 149 - 154
    • Ernst Althaus, Bernd Becker, Daniel Dumitriu, Stefan Kupferschmid
      Integration of an LP solver into interval constraint propagation
      2011 Int'l Conf. on Combinatorial optimization and applications, Springer, Seiten: 343 - 356
    • Matthew Lewis, Paolo Marin, Tobias Schubert, Massimo Narizzano, Bernd Becker, Enrico Giunchiglia
      Parallel QBF Solving with Advanced Knowledge Sharing
      2011 Fundamenta Informaticae, Band: 107, Nummer: 2-3, Seiten: 139 - 166
    • Erika Ábrahám, Tobias Schubert, Bernd Becker, Martin Fränzle, Christian Herde
      Parallel SAT Solving in Bounded Model Checking
      2011 Journal of Logic and Computation, Band: 21, Nummer: 1, Seiten: 5 - 21
    • Stefan Kupferschmid, Bernd Becker, Tino Teige, Martin Fränzle
      Proof Certificates and Non-linear Arithmetic Constraints
      2011 IEEE Design and Diagnostics of Electronic Circuits and Systems, Seiten: 429 - 434
    • Ralf Wimmer, Ernst Moritz Hahn, Holger Hermanns, Bernd Becker
      Reachability Analysis for Incomplete Networks of Markov Decision Processes
      2011 Int'l Conf. on Formal Methods and Models for Co-Design, IEEE Computer Society Press, Seiten: 151 - 160
    • Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker
      SAT-Based Analysis of Sensitisable Paths
      2011 IEEE Design and Diagnostics of Electronic Circuits and Systems, Seiten: 93 - 98
    • Bettina Braitling, Ralf Wimmer, Bernd Becker, Nils Jansen, Erika Ábrahám
      SMT-based Counterexample Generation for Markov Chains
      2011 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Offis Oldenburg, Band: 14, Seiten: 19 - 28

    2010

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    • Christian Miller, Karina Gitina, Christoph Scholl, Bernd Becker
      Bounded Model Checking of Incomplete Networks of Timed Automata
      2010 Int'l Workshop on Microprocessor Test and Verification, IEEE Computer Society, Band: 11, Seiten: 61 - 66
    • Stefan Kupferschmid, Matthew Lewis, Tobias Schubert, Bernd Becker
      Incremental Preprocessing Methods for use in BMC
      2010 Int'l Workshop on Hardware Verification
    • Christian Miller, Stefan Kupferschmid, Bernd Becker
      Exploiting Craig Interpolants in Bounded Model Checking for Incomplete Designs
      2010 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Band: 13, Seiten: 77 - 86
    • Tobias Nopper, Christian Miller, Matthew Lewis, Bernd Becker, Christoph Scholl
      SAT modulo BDD - A Combined Verification Approach for Incomplete Designs
      2010 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Band: 13, Seiten: 107 - 116
    • Pepijn Crouzen, Ernst Moritz Hahn, Holger Hermanns, Abhishek Dhama, Oliver Theel, Ralf Wimmer, Bettina Braitling, Bernd Becker
      Bounded Fairness for Probabilistic Distributed Algorithms
      AVACS Technical Report, Band: 57, 2010
    • Ralf Wimmer, Bernd Becker
      Correctness Issues of Symbolic Bisimulation Computation for Markov Chains
      2010 Int'l GI/ITG Conference on “Measurement, Modelling and Evaluation of Computing Systems”, Springer-Verlag, Band: 5987, Seiten: 287 - 301
    • Erika Ábrahám, Nils Jansen, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker
      DTMC Model Checking by SCC Reduction
      2010 Int'l Conf. on Quantitative Evaluation of Systems, IEEE Computer Society, Seiten: 37 - 46
    • Christian Miller, Stefan Kupferschmid, Matthew Lewis, Bernd Becker
      Encoding Techniques, Craig Interpolants and Bounded Model Checking for Incomplete Designs
      2010 Theory and Applications of Satisfiability Testing, Springer, Seiten: 194 - 208
    • Natalia Kalinnik, Erika Ábrahám, Tobias Schubert, Ralf Wimmer, Bernd Becker
      Exploiting Different Strategies for the Parallelization of an SMT Solver
      2010 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Fraunhofer Verlag, Seiten: 97 - 106
    • Ilia Polian, Bernd Becker
      Fault Models and Test Algorithms for Nanoscale Technologies
      2010 it - Information Technology, Band: 52, Nummer: 4, Seiten: 189 - 194
    • Ralf Wimmer, Bettina Braitling, Bernd Becker, Ernst Moritz Hahn, Pepijn Crouzen, Holger Hermanns, Abhishek Dhama, Oliver Theel
      Symblicit Calculation of Long-Run Averages for Concurrent Probabilistic Systems
      2010 Int'l Conf. on Quantitative Evaluation of Systems, IEEE Computer Society, Seiten: 27 - 36
    • Alexander Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
      Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis
      2010 International Journal of Parallel Programming, Band: 38, Nummer: 3-4, Seiten: 185 - 202
    • Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich
      Variation-Aware Fault Modeling
      2010 IEEE Asian Test Symp., Seiten: 87 - 93

    2009

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    • Alexander Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
      Dynamic Compaction in SAT-Based ATPG
      2009 IEEE Asian Test Symp.
    • Alexander Czutro, Bernd Becker, Ilia Polian
      Performance Evaluation of SAT-Based ATPG on Multi-Core Architectures
      2009 IEEE East-West Design & Test Symposium
    • Marc Hunger, Sybille Hellebrand, Alexander Czutro, Ilia Polian, Bernd Becker
      Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung
      2009 GMM/ITG-Fachtagung “Zuverlässigkeit und Entwurf”
    • Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian
      SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges
      2009 ACM Trans. on Design Automation of Electronic Systems, Band: 14, Nummer: 4, Seiten: 56:1 - 56:21
    • Natalia Kalinnik, Tobias Schubert, Erika Ábrahám, Ralf Wimmer, Bernd Becker
      Picoso - A Parallel Interval Constraint Solver
      2009 Int'l Conf. on Parallel and Distributed Processing Techniques and Applications, CSREA Press, Seiten: 473 - 479
    • Marc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, Bernd Becker
      ATPG-Based Grading of Strong Fault-Secureness
      2009 IEEE Int'l Online Testing Symp.
    • Nicolas Houarche, Alejandro Czutro, Mariane Comte, Piet Engelke, Ilia Polian, Bernd Becker, Michel Renovell
      An Electrical Model for the Fault Simulation of Small-Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects
      2009 VLSI Test Symp.
    • Nicolas Houarche, Alejandro Czutro, Mariane Comte, Piet Engelke, Ilia Polian, Bernd Becker, Michel Renovell
      Deriving an Electrical Model for Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects
      2009 Latin-American Test Workshop
    • Alejandro Czutro, Bernd Becker, Ilia Polian
      Performance Evaluation of SAT-Based Automatic Test Pattern Generation on Multi-Core Architectures
      2009 GI/ITG Int'l Conf. on Architecture of Computing Systems, Many-Cores Workshop
    • Alejandro Czutro, Bernd Becker, Ilia Polian
      Performance Evaluation of SAT-Based ATPG on Multi-Core Architectures
      2009 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
      TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis
      2009 Int'l Conf. on VLSI Design, Seiten: 227 - 232
    • Paolo Marin, Matthew Lewis, Massimo Narizzano, Tobias Schubert, Enrico Giunchiglia, Bernd Becker
      Comparison of Knowledge Sharing Strategies in a Parallel QBF Solver
      2009 High-Performance Computing and Simulation Conference, Seiten: 161 - 167
    • Eckard Böde, Marc Herbstritt, Holger Hermanns, Sven Johr, Thomas Peikenkamp, Reza Pulungan, Jan Rakow, Ralf Wimmer, Bernd Becker
      Compositional Dependability Evaluation for Statemate
      2009 IEEE Trans. on Software Engineering, Band: 35, Nummer: 2, Seiten: 274 - 292
    • Ralf Wimmer, Bettina Braitling, Bernd Becker
      Counterexample Generation for Discrete-time Markov Chains using Bounded Model Checking
      2009 Int'l Conf. on Verification, Model Checking and Abstract Interpretation, Springer-Verlag, Band: 5403, Seiten: 366 - 380
    • Matthew Lewis, Tobias Schubert, Bernd Becker
      DPLL-based Reasoning in a Multi-Core Environment
      2009 Int'l Workshop on Microprocessor Test and Verification
    • Abhishek Dhama, Oliver Theel, Pepijn Crouzen, Holger Hermanns, Ralf Wimmer, Bernd Becker
      Dependability Engineering of Silent Self-Stabilizing Systems
      2009 Int'l Symp. on Stabilization, Safety, and Security of Distributed Systems, Springer-Verlag, Band: 5873, Seiten: 238 - 253
    • Paolo Marin, Matthew Lewis, Tobias Schubert, Massimo Narizzano, Bernd Becker, Enrico Giunchiglia
      Evaluation of Knowledge Sharing Strategies in a Parallel QBF Solver
      2009 RCRA International Workshop on Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion
    • Tobias Schubert, Matthew Lewis, Bernd Becker
      PaMiraXT: Parallel SAT Solving with Threads and Message Passing
      2009 Journal on Satisfiability, Boolean Modeling, and Computation, Band: 6, Seiten: 203 - 222
    • Matthew Lewis, Paolo Marin, Tobias Schubert, Massimo Narizzano, Bernd Becker, Enrico Giunchiglia
      PaQuBE: Distributed QBF Solving with Advanced Knowledge Sharing
      2009 Int'l Conf. on Theory and Applications of Satisfiability Testing, Band: 5584, Seiten: 509 - 523
    • Stefan Kupferschmid, Tino Teige, Bernd Becker, Martin Fränzle
      Proofs of Unsatisfiability for mixed Boolean and Non-linear Arithmetic Constraint Formulae
      2009 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Seiten: 27 - 36
    • Matthew Lewis, Tobias Schubert, Bernd Becker
      QMiraXT - A Multithreaded QBF Solver
      2009 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”
    • Stefan Hillebrecht, Ilia Polian, P. Ruther, S. Herwik, Bernd Becker, Oliver Paul
      Reliability Characterization of Interconnects in CMOS Integrated Circuits Under Mechanical Stress
      2009 Int'l Reliability Physics Symp.

    2008

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    • Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker
      A Simulator of Small-Delay Faults Caused by Resistive-Open Defects
      2008 IEEE European Test Symp., Seiten: 113 - 118
    • Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
      TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis
      2008 edaWorkshop
    • Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker
      On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
      2008 IEEE Trans. on CAD, Band: 27, Nummer: 2, Seiten: 327 - 338
    • Damian Nowroth, Ilia Polian, Bernd Becker
      A Study of Cognitive Resilience in a JPEG Compressor
      2008 Int'l Conf. on Dependable Systems and Networks, Seiten: 32 - 41
    • Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
      Automatic Test Pattern Generation for Interconnect Open Defects
      2008 VLSI Test Symp., Seiten: 181 - 186
    • Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
      Automatic Test Pattern Generation for Interconnect Open Defects
      2008 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Ilia Polian, Yusuke Nakamura, Piet Engelke, Stefan Hillebrecht, Kohei Miyase, Seiji Kajihara, Bernd Becker, Xiaoqing Wen
      Diagnose realistischer Defekte mit Hilfe des X-Fehlermodells
      2008 GMM/GI/ITG Reliability and Design Conf., Seiten: 155 - 156
    • Ilia Polian, Yusuke Nakamura, Piet Engelke, Stefan Spinner, Kohei Miyase, Seiji Kajihara, Bernd Becker, Xiaoqing Wen
      Diagnosis of Realistic Defects Based on the X-Fault Model
      2008 IEEE Design and Diagnostics of Electronic Circuits and Systems, Seiten: 263 - 268
    • Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
      Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model
      2008 Int'l Test Conf., Seiten: 1 - 10
    • Thomas Eschbach, Bernd Becker
      Interactive Circuit Diagram Visualization
      2008 Computer Graphics and Imaging, ACTA Press, Seiten: 218 - 223
    • Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, X. Tang, Bernd Becker
      No Free Lunch in Error Protection?
      2008 Workshop on Dependable and Secure Nanocomputing
    • Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, X. Tang, Bernd Becker
      On Reducing Circuit Malfunctions Caused by Soft Errors
      2008 Int'l Symp. on Defect and Fault Tolerance, Seiten: 245 - 253
    • Ralf Wimmer, Alexander Kortus, Marc Herbstritt, Bernd Becker
      Probabilistic Model Checking and Reliability of Results
      2008 IEEE Design and Diagnostics of Electronic Circuits and Systems, IEEE Computer Science Press, Seiten: 207 - 212
    • Bernd Becker, Marc Herbstritt, Natalia Kalinnik, Matthew Lewis, Juri Lichtner, Tobias Nopper, Ralf Wimmer
      Propositional Approximations for Bounded Model Checking of Partial Circuit Designs
      2008 IEEE Int'l Conf. on Computer Design, IEEE Computer Society Press, Seiten: 52 - 59
    • Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker
      Resistive Bridging Fault Simulation of Industrial Circuits
      2008 Conf. on Design, Automation and Test in Europe, Seiten: 628 - 633
    • Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker
      Resistive Bridging Fault Simulation of Industrial Circuits
      2008 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Ilia Polian, Sudhakar M. Reddy, Bernd Becker
      Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors
      2008 IEEE Int'l Symp. on VLSI, Seiten: 257 - 262
    • Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker
      Selective Hardening in Early Design Steps
      2008 IEEE European Test Symp., Seiten: 185 - 190
    • Bernd Becker, Paul Molitor
      Technische Informatik: Eine einführende Darstellung
      Oldenbourg Wissenschaftsverlag, 2008
    • Ralf Wimmer, Alexander Kortus, Marc Herbstritt, Bernd Becker
      The Demand for Reliability in Probabilistic Verification
      2008 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Shaker Verlag, Seiten: 99 - 108

    2007

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    • Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
      Power Droop Testing
      2007 IEEE Design & Test of Computers, Band: 24, Nummer: 3, Seiten: 276 - 284
    • Marc Herbstritt, Bernd Becker, Erika Ábrahám, Christian Herde
      On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata
      2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, IEEE Computer Society, Seiten: 391 - 396
    • Matthew Lewis, Tobias Schubert, Bernd Becker
      Multithreaded SAT Solving
      2007 ASP Design Automation Conf., Seiten: 926 - 921
    • Bernd Becker, Andreas Podelski, Werner Damm, Martin Fränzle, Ernst-Rüdiger Olderog, Reinhard Wilhelm
      SFB/TR 14 AVACS – Automatic Verification and Analysis of Complex Systems (Der Sonderforschungsbereich/Transregio 14 AVACS – Automatische Verifikation und Analyse komplexer Systeme)
      2007 it - Information Technology, Oldenbourg Wissenschaftsverlag GmbH, Band: 49, Nummer: 2, Seiten: 118 - 126
    • Stefan Spinner, Ilia Polian, Bernd Becker, P. Ruther, Oliver Paul
      A System for the Calibration and Reliability Testing of MEMS Devices Under Mechanical Stress
      2007 VDE Microsystem Technology Congress, Seiten: 861 - 864
    • John P. Hayes, Ilia Polian, Bernd Becker
      An Analysis Framework for Transient-Error Tolerance
      2007 VLSI Test Symp., Seiten: 249 - 255
    • Marc Herbstritt, Vanessa Struve, Bernd Becker
      Application of Lifting in Partial Design Analysis
      2007 Int'l Workshop on Microprocessor Test and Verification, IEEE Computer Society, Seiten: 33 - 38
    • Tobias Nopper, Christoph Scholl, Bernd Becker
      Computation of Minimal Counterexamples by Using Black Box Techniques and Symbolic Methods
      2007 IEEE Int'l Conf. on Computer-Aided Design, IEEE Computer Society Press, Seiten: 273 - 280
    • Ilia Polian, John P. Hayes, Bernd Becker
      Cost-Efficient Circuit Hardening Based on Critical Soft Error Rate
      2007 IEEE Workshop on RTL ATPG and DfT
    • Ilia Polian, John P. Hayes, Damian Nowroth, Bernd Becker
      Ein kostenbegrenzter Ansatz zur Reduktion der transienten Fehlerrate
      2007 GMM/GI/ITG Reliability and Design Conf., Seiten: 183 - 184
    • Ralf Wimmer, Marc Herbstritt, Bernd Becker
      Forwarding, Splitting, and Block Ordering to Optimize BDD-based Bisimulation Computation
      2007 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Shaker Verlag, Seiten: 203 - 212
    • Ilia Polian, Damian Nowroth, Bernd Becker
      Identification of Critical Errors in Imaging Applications
      2007 Int'l On-Line Test Symp., Seiten: 201 - 202
    • Bernd Becker, Christian Dax, Jochen Eisinger, Felix Klaedtke
      LIRA: Handling Constraints of Linear Arithmetics over the Integers and the Reals
      2007 Int'l Conf. on CAV, Springer-Verlag, Seiten: 312 - 315
    • Marc Herbstritt, Bernd Becker
      On Combining 01X-Logic and QBF
      2007 Int'l Conf. on Computer Aided Systems Theory, Springer Verlag, Seiten: 531 - 538
    • Ralf Wimmer, Marc Herbstritt, Bernd Becker
      Optimization Techniques for BDD-based Bisimulation Minimization
      2007 Great Lakes Symp. on VLSI, ACM Press, Seiten: 405 - 410
    • Bernd Becker, Jochen Eisinger, Felix Klaedtke
      Parallelization of Decision Procedures for Automatic Structures
      2007 Workshop on Omega-Automata
    • Piet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker
      SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges
      2007 IEEE Asian Test Symp., Seiten: 433 - 438
    • Stefan Spinner, Jie Jiang, Ilia Polian, Piet Engelke, Bernd Becker
      Simulating Open-Via Defects
      2007 IEEE Asian Test Symp., Seiten: 265 - 270
    • Ralf Wimmer, Alexander Kortus, Marc Herbstritt, Bernd Becker
      Symbolic Model Checking for DTMCs with Exact and Inexact Arithmetic
      AVACS Technical Report, Nummer: 30, 2007
    • Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich
      Test und Zuverlässigkeit Nanoelektronischer Systeme
      2007 GMM/GI/ITG Reliability and Design Conf., Seiten: 139 - 140
    • Ralf Wimmer, Holger Hermanns, Marc Herbstritt, Bernd Becker
      Towards Symbolic Stochastic Aggregation
      AVACS Technical Report, Nummer: 16, 2007

    2006

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    • Ralf Wimmer, Tobias Nopper, Marc Herbstritt, Christoph Löffler, Bernd Becker
      Collaborative Exercise Management
      2006 World Conf. on E-Learning in Corporate, Government, Healthcare, and Higher Education, Association for the Advancement of Computing in Education (AACE), Seiten: 3127 - 3134
    • Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
      Power Droop Testing
      2006 Int'l Conf. on Computer Design, Seiten: 243 - 250
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
      Simulating Resistive Bridging and Stuck-At Faults
      2006 IEEE Trans. on CAD, Band: 25, Nummer: 10, Seiten: 2181 - 2192
    • Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker
      Analyzing the memory effect of resistive open in CMOS random logic
      2006 Int'l Conf. on Design and Test of Integrated Systems in Nanoscale Technology, Seiten: 251 - 256
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
      Automatic Test Pattern Generation for Resistive Bridging Faults
      2006 Jour. Electronic Testing, Band: 22, Nummer: 1, Seiten: 61 - 69
    • Erika Ábrahám, Marc Herbstritt, Bernd Becker, Martin Steffen
      Memory-aware Bounded Model Checking for Linear Hybrid Systems
      2006 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Fraunhofer IIS/EAS, Seiten: 153 - 162
    • Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke
      X-Masking During Logic BIST and Its Impact on Defect Coverage
      2006 IEEE Trans. on VLSI Systems, Band: 14, Nummer: 2, Seiten: 193 - 202
    • Jan Reineke, Björn Wachter, Stephan Thesing, Reinhard Wilhelm, Jochen Eisinger, Ilia Polian, Bernd Becker
      A Definition and Classification of Timing Anomalies
      2006 Int'l Workshop on Worst-Case Execution Time
    • John P. Hayes, Ilia Polian, Bernd Becker
      A Model for Transient Faults in Logic Circuits
      2006 Int'l Design and Test Workshop
    • Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker
      A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency
      2006 IEEE Asian Test Symp., Seiten: 273 - 278
    • Stefan Spinner, M. Doelle, P. Ruther, Ilia Polian, Oliver Paul, Bernd Becker
      A System for Electro-Mechanical Reliability Testing of MEMS Devices
      2006 Int'l Symp. for Testing and Failure Analysis, Seiten: 147 - 152
    • Marc Herbstritt, Bernd Becker, Christoph Scholl
      Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs
      2006 Int'l Workshop on Microprocessor Test and Verification, IEEE Computer Society, Seiten: 37 - 44
    • Marc Herbstritt, Ralf Wimmer, Thomas Peikenkamp, Eckard Böde, Michael Adelaide, Sven Johr, Holger Hermanns, Bernd Becker
      Analysis of Large Safety-Critical Systems: A quantitative Approach
      AVACS Technical Report, Band: 8, 2006
    • Jochen Eisinger, Ilia Polian, Bernd Becker, Alexander Metzner, Stephan Thesing, Reinhard Wilhelm
      Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis
      2006 IEEE Design and Diagnostics of Electronic Circuits and Systems, IEEE Computer Society, Seiten: 15 - 20
    • Erika Ábrahám, Marc Herbstritt, Bernd Becker, Martin Steffen
      Bounded Model Checking with Parametric Data Structures
      2006 BMC, Band: 174, Nummer: 3, Seiten: 3 - 16
    • Eckard Böde, Marc Herbstritt, Holger Hermanns, Sven Johr, Thomas Peikenkamp, Reza Pulungan, Ralf Wimmer, Bernd Becker
      Compositional Performability Evaluation for STATEMATE
      2006 Int'l Conf. on Quantitative Evaluation of Systems, IEEE Computer Society, Seiten: 167 - 178
    • Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich
      DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems)
      2006 it - Information Technology, Band: 48, Nummer: 5, Seite: 304
    • Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker
      Delta-IddQ Testing of Resistive Short Defects
      2006 IEEE Asian Test Symp., Seiten: 63 - 68
    • Stefan Spinner, J. Bartholomeyczik, Bernd Becker, M. Doelle, Oliver Paul, Ilia Polian, P. Roth, K. Seitz, P. Ruther
      Electromechanical Reliability Testing of Three-Axial Force Sensors
      2006 Design, Test, Integration and Packaging of MEMS/MOEMS, Seiten: 77 - 82
    • Piet Engelke, Ilia Polian, Hans Manhaeve, Bernd Becker
      IddQ Testing of Resistive Bridging Defects
      2006 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 123 - 124
    • Ilia Polian, Bernd Becker, M. Nakasato, S. Ohtake, Hideo Fujiwara
      Low-Cost Hardening of Image Processing Applications Against Soft Errors
      2006 Int'l Symp. on Defect and Fault Tolerance, Seiten: 274 - 279
    • Ralf Wimmer, Marc Herbstritt, Bernd Becker
      Minimization of Large State Spaces using Symbolic Branching Bisimulation
      2006 IEEE Design and Diagnostics of Electronic Circuits and Systems, IEEE Computer Society Press, Seiten: 9 - 14
    • Thomas Eschbach, Wolfgang Günther, Bernd Becker
      Orthogonal Hypergraph Drawing for Improved Visibility
      2006 Journal of Graph Algorithms and Applications, Band: 10, Nummer: 2, Seiten: 141 - 157
    • Erika Ábrahám, Tobias Schubert, Bernd Becker, Martin Fränzle, Christian Herde
      Parallel SAT-Solving in Bounded Model Checking
      2006 Int'l Workshop on Parallel and Distributed Methods in Verification, Springer-Verlag, Band: 4346, Seiten: 301 - 315
    • Ilia Polian, Bernd Becker, M. Nakasato, S. Ohtake, Hideo Fujiwara
      Period of Grace: A New Paradigm for Efficient Soft Error Hardening
      2006 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Stefan Spinner, J. Bartholomeyczik, Bernd Becker, M. Doelle, Oliver Paul, Ilia Polian, R. Roth, K. Seitz, P. Ruther
      Reliability Testing of Three-Dimensional Silicon Force Sensors
      2006 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Ralf Wimmer, Marc Herbstritt, Holger Hermanns, Kelley Strampp, Bernd Becker
      Sigref - A Symbolic Bisimulation Tool Box
      2006 Int'l Symp. on Automated Technology for Verification and Analysis, Springer-Verlag, Band: 4218, Seiten: 477 - 492

    2005

    Icon: top nach oben zur Jahresübersicht
    • Marc Herbstritt, Bernd Becker
      On SAT-based Bounded Invariant Checking of Blackbox Designs
      2005 Int'l Workshop on Microprocessor Test and Verification, IEEE Computer Society, Seiten: 23 - 28
    • Martina Welte, Thomas Eschbach, Bernd Becker
      Automated Text Extraction And Indexing Of Video Presentation Recordings For Keyword Search Via A Web Interface
      2005 Workshop eLectures - Einsatzmöglichkeiten, Herausforderungen und Forschungsperspektiven, Logos Verlag Berlin
    • Matthew Lewis, Tobias Schubert, Bernd Becker
      Speedup Techniques Utilized in Modern SAT Solvers - An Analysis in the MIRA Environment
      2005 Theory and Applications of Satisfiability Testing, Springer, Band: 3569, Seiten: 437 - 443
    • Ilia Polian, Alejandro Czutro, Bernd Becker
      Evolutionary Optimization in Code-Based Test Compression
      2005 Conf. on Design, Automation and Test in Europe, Seiten: 1124 - 1129
    • Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
      Modeling feedback bridging faults with non-zero resistance.
      2005 Jour. Electronic Testing, Band: 21, Nummer: 1, Seiten: 57 - 69
    • John P. Hayes, Ilia Polian, Thomas Fiehn, Bernd Becker
      A Family of Logical Fault Models for Reversible Circuits
      2005 IEEE European Test Symp., Seiten: 65 - 70
    • Ilia Polian, John P. Hayes, Thomas Fiehn, Bernd Becker
      A Family of Logical Fault Models for Reversible Circuits
      2005 IEEE Asian Test Symp., Seiten: 422 - 427
    • Tobias Schubert, Bernd Becker
      A Hardware Lab Anywhere at Any Time
      2005 Journal of Systemics, Cybernetics, and Informatics: JSCI, Band: 2, Nummer: 6
    • Sandip Kundu, Matthew Lewis, Ilia Polian, Bernd Becker
      A Soft Error Emulation System for Logic Circuits
      2005 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 10 - 14
    • Sandip Kundu, Matthew Lewis, Ilia Polian, Bernd Becker
      A Soft Error Emulation System for Logic Circuits
      2005 Conf. on Design of Circuits and Integrated Systems, Seite: 137
    • M. Doelle, Stefan Spinner, P. Ruther, Ilia Polian, Oliver Paul, Bernd Becker
      A System for Determining the Impact of Mechanical Stress on the Reliability of MEMS
      2005 IEEE European Test Symp., Seiten: 57 - 61
    • M. Doelle, Stefan Spinner, P. Ruther, Ilia Polian, Oliver Paul, Bernd Becker
      A System for Determining the Impact of Mechanical Stress on the Reliability of MEMS
      2005 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 88 - 89
    • Tobias Schubert, Bernd Becker
      Accelerating Boolean SAT Engines Using Hyper-Threading Technology
      2005 Asian Applied Computing Conf.
    • Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker
      An Unified Fault Model and Test Generation Procedure for Interconnect Opens and Bridges
      2005 IEEE European Test Symp., Seiten: 22 - 27
    • Martina Welte, Thomas Eschbach, Bernd Becker
      Automated Text Extraction And Indexing Of Video Presentation Recordings For Keyword Search Via A Web Interface
      2005 AACE World Conf. on E-Learning in Corporate, Government, Healthcare, and Higher Education, AACE Press, Seiten: 3200 - 3205
    • Bernd Becker, Markus Behle, Friedrich Eisenbrand, Ralf Wimmer
      BDDs in a Branch & Cut Framework
      2005 Int'l Workshop on Efficient and Experimental Algorithms, Springer Verlag, Band: 3503, Seiten: 452 - 463
    • Tobias Schubert, Bernd Becker
      Knowledge Sharing in a Microcontroller based Parallel SAT Solver
      2005 Int'l Conf. on Parallel and Distributed Processing Techniques and Applications
    • Tobias Schubert, Bernd Becker
      Lemma Exchange in a Microcontroller based Parallel SAT Solver
      2005 IEEE Int'l Symp. on VLSI
    • Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
      Modeling feedback bridging faults with non-zero resistance
      2005 Jour. Electronic Testing, Band: 21, Nummer: 1, Seiten: 57 - 69
    • Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker
      On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
      2005 IEEE Asian Test Symp., Seiten: 266 - 269
    • Erika Ábrahám, Bernd Becker, Felix Klaedtke, Martin Steffen
      Optimizing bounded model checking for linear hybrid systems
      2005 Int'l Conf. on Verification, Model Checking and Abstract Interpretation, Springer-Verlag, Band: 3385, Seiten: 396 - 412
    • Thomas Eschbach, Wolfgang Günther, Bernd Becker
      Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases
      2005 Int'l Conf. on VLSI Design, Seiten: 433 - 438
    • Tobias Schubert, Bernd Becker, Matthew Lewis
      PaMira - A Parallel SAT Solver with Knowledge Sharing
      2005 Int'l Workshop on Microprocessor Test and Verification, IEEE Computer Society, Band: 00, Seiten: 29 - 36
    • Ilia Polian, Sandip Kundu, Jean-Marc Galliere, Piet Engelke, Michel Renovell, Bernd Becker
      Resistive Bridge Fault Model Evolution From Conventional to Ultra Deep Submicron Technologies
      2005 VLSI Test Symp., Seiten: 343 - 348
    • Jochen Eisinger, Peter Winterer, Bernd Becker
      Securing Wireless Networks in a University Environment
      2005 IEEE Int'l Conf. on Pervasive Computing and Communications Workshops, IEEE Computer Society, Seiten: 312 - 316
    • Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
      Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
      2005 IEEE Design and Diagnostics of Electronic Circuits and Systems, Seiten: 43 - 48
    • Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
      Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
      2005 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 16 - 20
    • Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
      Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
      2005 IEEE Int'l Workshop on Current and Defect-Based Testing, Seiten: 43 - 48
    • Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker
      Transient Fault Characterization in Dynamic Noisy Environments
      2005 Int'l Test Conf., Seiten: 10 pp. - 1048

    2004

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    • Erika Ábrahám, Bernd Becker, Felix Klaedtke, Martin Steffen
      Optimizing Bounded Model Checking for Linear Hybrid Systems
      , Nummer: 214, 2004
    • Marc Herbstritt, Thomas Kmieciak, Bernd Becker
      On the Impact of Structural Circuit Partitioning on SAT-based Combinational Circuit Verification
      2004 Int'l Workshop on Microprocessor Test and Verification, IEEE Computer Society, Seiten: 50 - 55
    • Marc Herbstritt, Thomas Kmieciak, Bernd Becker
      Circuit Partitioning for SAT-based Combinational Circuit Verification -- A Case Study
      , Nummer: 206, 2004
    • Ilia Polian, Bernd Becker, Alejandro Czutro
      Compression Methods for Path Delay Fault Test Pair Sets: A Comparative Study
      2004 IEEE European Test Symp., Seiten: 263 - 264
    • Matthew Lewis, Tobias Schubert, Bernd Becker
      Early Conflict Detection Based BCP for SAT Solving
      2004 Int'l Conf. on Theory and Applications of Satisfiability Testing, Seiten: 29 - 36
    • Ilia Polian, Irith Pomeranz, Sudhakar M. Reddy, Bernd Becker
      On the use of maximally dominating faults in n-detection test generation
      2004 IEE Proceedings Computers and Digital Techniques, Band: 151, Nummer: 3, Seiten: 235 - 244
    • Ilia Polian, Bernd Becker
      Scalable Delay Fault BIST For Use With Low-Cost ATE
      2004 Jour. Electronic Testing, Band: 20, Nummer: 2, Seiten: 181 - 197
    • Yuyi Tang, Hans-Joachim Wunderlich, Harald Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
      X-masking during logic BIST and its impact on defect coverage
      2004 IEEE Int'l Workshop on Test Resource Partitioning, Seiten: 442 - 451
    • Tobias Schubert, Bernd Becker
      A Distributed SAT Solver for Microchip Microcontroller
      2004 Workshop on Parallel Systems and Algorithms
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
      Automatic test pattern generation for resistive bridging faults
      2004 IEEE European Test Symp., Seiten: 160 - 165
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
      Automatic test pattern generation for resistive bridging faults
      2004 IEEE Int'l Workshop on Current and Defect-Based Testing, Seiten: 89 - 94
    • Bernd Becker, Markus Behle, Friedrich Eisenbrand, Martin Fränzle, Marc Herbstritt, Christian Herde, Jörg Hoffmann, Daniel Kröning, Bernhard Nebel, Ilia Polian, Ralf Wimmer
      Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems
      2004 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Shaker Verlag, Seiten: 65 - 75
    • Matthew Lewis, Tobias Schubert, Bernd Becker
      Early Conflict Detection Based SAT Solving
      2004 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”
    • Thomas Eschbach, Wolfgang Günther, Bernd Becker
      Orthogonal Hypergraph Routing for Improved Visibility
      2004 Great Lakes Symp. on VLSI, Seiten: 385 - 388
    • Tobias Schubert, Bernd Becker
      PICHAFF2 - A Hierarchical Parallel SAT Solver
      2004 Int'l Workshop on Microprocessor Test and Verification
    • Tobias Schubert, Bernd Becker
      Parallel SAT Solving with Microcontrollers
      2004 Asian Applied Computing Conf.
    • Thomas Eschbach, Rolf Drechsler, Bernd Becker
      Placement and Routing Optimization for Circuits Derived from BDDs
      2004 IEEE Int'l Symp. on Circuits and Systems, Seiten: V229 - V232
    • John P. Hayes, Ilia Polian, Bernd Becker
      Testing for Missing-Gate Faults in Reversible Circuits
      2004 IEEE Asian Test Symp., Seiten: 100 - 105
    • Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
      The Pros and Cons of Very-Low-Voltage Testing: An Analysis Based on Resistive Short Defects
      2004 VLSI Test Symp., Seiten: 171 - 178
    • Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
      The Pros and Cons of Very-Low-Voltage Testing: An Analytical View
      2004 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 149 - 153
    • Yuyi Tang, Hans-Joachim Wunderlich, Harald Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
      X-masking during logic BIST and its impact on defect coverage
      2004 Int'l Test Conf., Seiten: 442 - 451

    2003

    Icon: top nach oben zur Jahresübersicht
    • Tobias Schubert, Bernd Becker
      PICHAFF: A Distributed SAT Solver for Microcontrollers
      2003 Euromicro Conf.
    • Thomas Eschbach, Wolfgang Günther, Bernd Becker
      Crossing Reduction for Orthogonal Circuit Visualization
      2003 Int'l Conf. on VLSI, CSREA Press, Seiten: 107 - 113
    • Marc Herbstritt, Bernd Becker
      Conflict-based Selection of Branching Rules
      2003 Int'l Conf. on Theory and Applications of Satisfiability Testing, Springer, Band: 2919, Seiten: 441 - 451
    • Marc Herbstritt, Bernd Becker
      Conflict-based Selection of Branching Rules in SAT-Algorithms
      2003 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Seiten: 189 - 198
    • Tobias Schubert, Bernd Becker
      A Hardware Lab Anywhere At Anytime
      2003 Int'l Conf. on Education and Information Systems: Technologies and Applications, Seiten: 130 - 135
    • Ilia Polian, Bernd Becker
      Configuring MISR-Based Two-Pattern BIST Using Boolean Satisfiability
      2003 IEEE Design and Diagnostics of Electronic Circuits and Systems, Seiten: 73 - 80
    • Tobias Schubert, Bernd Becker
      Das Mobile Hardware-Praktikum
      2003 European Conf. on Media in Higher Education
    • Ilia Polian, Bernd Becker, Sudhakar M. Reddy
      Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST
      2003 Conf. on Design, Automation and Test in Europe, Seiten: 1184 - 1185
    • Frank Schmiedle, Rolf Drechsler, Bernd Becker
      Exact Routing with Search Space Reduction
      2003 IEEE Trans. on Computers, Band: 52, Nummer: 6, Seiten: 815 - 825
    • Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
      Modelling Feedback Bridging Faults With Non-Zero Resistance
      2003 European Test Workshop, Seiten: 91 - 96
    • Ilia Polian, Bernd Becker
      Multiple Scan Chain Design for Two-Pattern Testing
      2003 Jour. Electronic Testing, Band: 19, Nummer: 1, Seiten: 37 - 48
    • Ilia Polian, Wolfgang Günther, Bernd Becker
      Pattern-Based Verification of Connections to Intellectual Property Cores
      2003 INTEGRATION, the VLSI Jour., Band: 35, Nummer: 1, Seiten: 25 - 44
    • Martin Keim, M. Martin, Bernd Becker, Rolf Drechsler, Paul Molitor
      Polynomial Formal Verification of Multipliers
      2003 Formal Methods in System Design, Band: 22, Nummer: 1, Seiten: 39 - 58
    • Ilia Polian, Bernd Becker
      Reducing ATE Cost in System-on-Chip
      2003 IFIP VLSI-SoC, Seiten: 337 - 342
    • Ilia Polian, Bernd Becker
      Reducing ATE Cost in System-on-Chip Test
      2003 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 34 - 37
    • Ilia Polian, Bernd Becker
      Reducing ATE Cost in System-on-Chip Test
      2003 IEEE Int'l Workshop on Test Resource Partitioning
    • J. Bradford, H. Delong, Ilia Polian, Bernd Becker
      Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
      2003 Jour. Electronic Testing, Band: 19, Nummer: 4, Seiten: 387 - 395
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
      Simulating Resistive Bridging Faults
      2003 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 92 - 97
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
      Simulating Resistive Bridging and Stuck-At Faults
      2003 Int'l Test Conf., Seiten: 1051 - 1059
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
      Simulating Resistive Bridging and Stuck-at Faults
      2003 IEEE Int'l Workshop on Current and Defect-Based Testing, Seiten: 49 - 56
    • Ilia Polian, Wolfgang Günther, Bernd Becker
      The Case For 2-POF
      2003 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Seiten: 164 - 173
    • Ilia Polian, Wolfgang Günther, Bernd Becker
      The Case For 2-POF
      2003 IEEE Design and Diagnostics of Electronic Circuits and Systems, Seiten: 291 - 292

    2002

    Icon: top nach oben zur Jahresübersicht
    • Christoph Scholl, Bernd Becker
      Checking Equivalence for Circuits Containing Incompletely Specified Boxes
      2002 Int'l Conf. on Computer Design, Seite: 56
    • Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker
      Crossing Reduction by Windows Optimization
      2002 Int'l Symp. on Graph Drawing, Band: 2528, Seiten: 285 - 294
    • Ilia Polian, Piet Engelke, Bernd Becker
      Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics
      2002 Int'l Symp. on Multi-Valued Logic, Seiten: 216 - 222
    • Christoph Scholl, Bernd Becker
      Equivalence Checking in the Presence of Incompletely Specified Boxes
      2002 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”
    • Ilia Polian, Irith Pomeranz, Bernd Becker
      Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests
      2002 IEEE Asian Test Symp., Seiten: 9 - 14
    • Ilia Polian, Irith Pomeranz, Bernd Becker
      Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests
      2002 European Test Workshop
    • Ilia Polian, Bernd Becker
      Optimal Bandwidth Allocation in Concurrent SoC Test Under Pin Number Constraints
      2002 Workshop on RTL and High Level Testing, Seiten: 12 - 17
    • J. Bradford, H. Delong, Ilia Polian, Bernd Becker
      Realistic Fault Simulation in an Industrial Setting
      2002 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker
      Sequential n-Detection Criteria: Keep It Simple!
      2002 IEEE Int'l Online Testing Workshop, Seiten: 189 - 190
    • J. Bradford, H. Delong, Ilia Polian, Bernd Becker
      Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
      2002 European Test Workshop, Seiten: 75 - 80
    • Ilia Polian, Bernd Becker
      Stop & Go BIST
      2002 IEEE Int'l Online Testing Workshop, Seiten: 147 - 151
    • Klaus-Jürgen Englert, Rolf Drechsler, Bernd Becker
      Verification of HDLs using Symbolic Set Representation
      2002 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”

    2001

    Icon: top nach oben zur Jahresübersicht
    • Wolfgang Günther, Andreas Hett, Bernd Becker
      Application of Linearly Transformed BDDs in Sequential Verification
      2001 ASP Design Automation Conf., Seiten: 91 - 96
    • Christoph Scholl, Bernd Becker
      Checking Equivalence for Partial Implementations
      2001 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Seiten: 31 - 43
    • Christoph Scholl, Bernd Becker
      Checking Equivalence for Partial Implementations
      2001 IEEE Design Automation Conference, IEEE Computer Society, Seiten: 238 - 243
    • Bernd Becker, Christoph Meinel, Masahiro Fujita, Fabio Somenzi
      Computer Aided Design and Test, BDDs versus SAT, Dagstuhl-Seminar-Report 297, 28.01.-02.02.01
      2001 Saarbrücken: Geschäftsstelle Schloss Dagstuhl
    • Christoph Scholl, Marc Herbstritt, Bernd Becker
      Don't Care Minimization of *BMDs: Complexity and Algorithms
      2001 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Seiten: 45 - 57
    • Ilia Polian, Wolfgang Günther, Bernd Becker
      Efficient Pattern-Based Verification of Connections to Intellectual Property Cores
      2001 IEEE Asian Test Symp., Seiten: 443 - 448
    • Ilia Polian, Wolfgang Günther, Bernd Becker
      Efficient Pattern-Based Verification of Connections to Intellectual Property Cores
      2001 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Seiten: I:111 - 120
    • Christoph Scholl, Marc Herbstritt, Bernd Becker
      Exploiting Don't Cares to Minimize *BMDs
      2001 IEEE Int'l Symp. on Circuits and Systems, Band: 5, Seiten: 191 - 194
    • Bernd Becker, Rolf Drechsler, Thomas Eschbach, Wolfgang Günther
      GREEDY IIP: Partitioning Large Graphs by Greedy Iterative Improvement
      2001 Euromicro Conf., Seiten: 54 - 60
    • Ilia Polian, Bernd Becker
      Multiple Scan Chain Design for Two-Pattern Testing
      2001 VLSI Test Symp., Seiten: 88 - 93
    • Ilia Polian, Bernd Becker
      Multiple Scan Chain Design for Two-Pattern Testing
      2001 Latin-American Test Workshop, Seiten: 156 - 161
    • Ilia Polian, Bernd Becker
      Multiple Scan Chain Design for Two-Pattern Testing
      2001 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Andreas Hett, Bernd Becker
      Supervised Dynamic Reordering in Model Checking
      2001 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Seiten: 21 - 30
    • Christoph Scholl, Bernd Becker, A. Brogle
      The Multiple Variable Order Problem for Binary Decision Diagrams: Theory and Practical Application
      2001 ASP Design Automation Conf., Seiten: 85 - 90
    • Frank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker
      Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics
      2001 Int'l Conf. on Computational Intelligence, Band: 2206, Seiten: 479 - 491
    • Frank Schmiedle, A. Markert, Bernd Becker
      XMaDRE: A Routing Environment with Visualization based on Ray-Tracing
      2001 Conf. on Design, Automation and Test in Europe

    2000

    Icon: top nach oben zur Jahresübersicht
    • Christoph Scholl, Bernd Becker
      Checking Equivalence for Partial Implementations
      , Nummer: 145, 2000
    • Christoph Scholl, Marc Herbstritt, Bernd Becker
      Exploiting Don't Cares to Minimize *BMDs
      , Nummer: 141, 2000
    • Piet Engelke, Bernd Becker, Martin Keim
      A Parameterizable Fault Simulator for Bridging Faults
      2000 European Test Workshop, Seiten: 63 - 68
    • Martin Keim, Piet Engelke, Bernd Becker
      A Parameterizable Fault Simulator for Bridging Faults
      2000 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Rolf Drechsler, Nicole Drechsler, Elke Mackensen, Tobias Schubert, Bernd Becker
      Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System
      2000 Euromicro Conf., Seiten: 1:425 - 431
    • Andreas Hett, Christoph Scholl, Bernd Becker
      Distance Driven Finite State Machine Traversal
      2000 IEEE Design Automation Conference, Seiten: 39 - 42
    • Frank Schmiedle, D. Unruh, Bernd Becker
      Exact Switchbox Routing with Search Space Reduction
      2000 Int'l Symp. on Physical Design, Seiten: 26 - 32
    • Tobias Schubert, Elke Mackensen, Nicole Drechsler, Rolf Drechsler, Bernd Becker
      Specialized Hardware for Implementation of Evolutionary Algorithms
      2000 Int'l Workshop on Boolean Problems, Seiten: 175 - 182
    • Tobias Schubert, Elke Mackensen, Nicole Drechsler, Rolf Drechsler, Bernd Becker
      Specialized Hardware for Implementation of Evolutionary Algorithms
      2000 Conf. on Genetic and Evolutionary Computation, Seite: 369
    • Andreas Hett, Christoph Scholl, Bernd Becker
      State Traversal guided by Hamming Distance Profiles
      2000 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, VDE Verlag, Seiten: 57 - 66
    • Rolf Drechsler, Wolfgang Günther, Bernd Becker
      Testability of Circuits Derived from Lattice Diagrams
      2000 Euromicro Conf., Seiten: 188 - 192
    • Rolf Drechsler, Wolfgang Günther, Bernd Becker
      Testability of Circuits Derived from Lattice Diagrams
      2000 Latin-American Test Workshop
    • Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
      Verification of Designs Containing Black Boxes
      2000 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”
    • Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
      Verification of Designs Containing Black Boxes
      2000 Euromicro Conf., Seiten: 100 - 105
    • Wolfgang Günther, R. Schönfeld, Bernd Becker, Paul Molitor
      k-Layer Straightline Crossing Minimization by Speeding up Sifting
      2000 Graph Drawing Conf., Springer Verlag, Band: 1984, Seiten: 253 - 258

    1999

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    • Christoph Scholl, Bernd Becker, A. Brogle
      Solving the Multiple Variable Order Problem for Binary Decision Diagrams by Use of Dynamic Reordering Techniques
      , Nummer: 130, 1999
    • Rolf Drechsler, Marc Herbstritt, Bernd Becker
      Grouping Heuristics for Word-level Decision Diagrams
      1999 IEEE Int'l Symp. on Circuits and Systems, Seiten: 411 - 415
    • Rolf Drechsler, Bernd Becker
      Probabilistic IP Verification
      1999 Int'l Workshop on Testing Embedded Core-based System-Chips
    • Nicole Drechsler, Rolf Drechsler, Bernd Becker
      A New Model for Multi-Objective Optimization in Evolutionary Algorithms
      1999 Int'l Conf. on Computational Intelligence, Springer Verlag, Band: 1625, Seiten: 108 - 117
    • Martin Keim, Ilia Polian, Harry Hengster, Bernd Becker
      A Scalable BIST Architecture for Delay Faults
      1999 European Test Workshop, Seiten: 98 - 103
    • Andreas Hett, Christoph Scholl, Bernd Becker
      A.MORE - A Multi-Operand BDD Package
      University of Freiburg, 1999
    • Martin Keim, Nicole Drechsler, Bernd Becker
      Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
      1999 ASP Design Automation Conf., Seiten: 315 - 318
    • Bernd Becker, Christoph Meinel, Shin-Ichi Minato, Fabio Somenzi
      Computer Aided Design and Test, Decision Diagrams - Concepts and Applications, (99041), Dagstuhl-Seminar-Report 229, 24.01.-29.1.1999
      1999 Saarbrücken: Geschäftsstelle Schloss Dagstuhl
    • Rolf Drechsler, Marc Herbstritt, Bernd Becker
      Grouping Heuristics for Word-level Decision Diagrams
      1999 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Shaker Verlag, Seiten: 41 - 50
    • Bernd Becker, Martin Keim, R. Krieger
      Hybrid Fault Simulation for Synchronous Sequential Circuit
      1999 Jour. Electronic Testing, Band: 3, Seiten: 219 - 238
    • Christoph Scholl, Bernd Becker
      On the Generation of Multiplexer Circuits for Pass Transistor Logic
      1999 Int'l Workshop on Logic Synth.
    • Christoph Scholl, Bernd Becker, A. Brogle
      Solving the Multiple Variable Order Problem for Binary Decision Diagram by Use of Dynamic Reordering Techniques
      1999 Int'l Workshop on Logic Synth.
    • Christoph Scholl, Bernd Becker, A. Brogle
      Solving the Multiple Variable Order Problem for Binary Decision Diagram by Use of Dynamic Reordering Techniques
      , Nummer: 130, 1999
    • Harry Hengster, Bernd Becker
      Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability -
      1999 Int'l Symp. on Defect and Fault Tolerance, Seiten: 268 - 275
    • Per Lindgren, Rolf Drechsler, Bernd Becker
      Synthesis of Pseudo Kronecker Lattice Diagrams
      1999 Int'l Conf. on Computer Design, Seiten: 307 - 310

    1998

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    • Martin Keim, Nicole Göckel, Rolf Drechsler, Bernd Becker
      Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
      , Nummer: 105/98, 1998
    • Rolf Drechsler, Bernd Becker
      Binary Decision Diagrams - Theory and Implementation
      Kluwer Academic Publishers, 1998
    • Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
      Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
      1998 European Test Workshop, Seiten: 141 - 142
    • Rolf Drechsler, Bernd Becker
      Graphenbasierte Funktionsdarstellung
      B.G. Teubner, 1998
    • Martin Keim, Bernd Becker
      Nearly Exact Signal Probabilities for Synchronous Sequential Circuits - An Experimental Analysis
      , Nummer: 106/98, 1998
    • Harry Hengster, Bernd Becker
      Synthesis of Fully Testable High Speed Circuits Derived from Decision Diagrams
      1998 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Harry Hengster, Bernd Becker
      Synthesis of Fully Testable High Speed Circuits Derived from Decision Diagrams
      1998 Int'l Workshop on Logic Synth., Seiten: 341 - 345
    • Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
      Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm
      1998 Int'l Symp. on Multi-Valued Logic, Seiten: 215 - 220
    • Martin Keim, Nicole Göckel, Rolf Drechsler, Bernd Becker
      Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm
      1998 Int'l Symp. on Multi-Valued Logic
    • Christoph Scholl, Bernd Becker, T. M. Weis
      Word-Level Decision Diagrams, WLCDs and Division
      1998 Int'l Conf. on CAD, Seiten: 672 - 677

    1997

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    • Nicole Göckel, Martin Keim, Rolf Drechsler, Bernd Becker
      A Genetic Algorithm for Sequential Circuit Test Generation based on Symbolic Fault Simulation
      1997 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Nicole Göckel, Martin Keim, Rolf Drechsler, Bernd Becker
      A Genetic Algorithm for Sequential Circuit Test Generation based on Symbolic Fault Simulation
      1997 European Test Workshop
    • Nicole Göckel, Rolf Drechsler, Bernd Becker
      A Multi-Layer Detailed Routing Approach based on Evolutionary Algorithms
      1997 Int'l Conf. on Evolutionary Computation, Seiten: 557 - 562
    • Rolf Drechsler, Nicole Göckel, Elke Mackensen, Bernd Becker
      BEA: Specialized Hardware for Implementation of Evolutionary Algorithms
      1997 Genetic Programming Conf., Seite: 491
    • Bernd Becker, Randy Bryant, Masahiro Fujita, Christoph Meinel
      Computer Aided Design and Test, Decision Diagrams - Concepts and Applications, (9705), Dagstuhl-Seminar-Report 166, 27.01.-31.1.1997
      1997 Saarbrücken: Geschäftsstelle Schloss Dagstuhl
    • Bernd Becker, Rolf Drechsler
      Decision Diagrams in Synthesis - Algorithms, Applications and Extensions -
      1997 Int'l Conf. on VLSI Design, Seiten: 46 - 50
    • Andreas Hett, Rolf Drechsler, Bernd Becker
      Fast and Efficient Construction of BDDs by reordering based Synthesis
      1997 European Design and Test Conf., Seiten: 168 - 175
    • Rolf Drechsler, Martin Keim, Bernd Becker
      Fault Simulation in Sequential Multi-Valued Logic Networks
      1997 Int'l Symp. on Multi-Valued Logic, Seiten: 145 - 150
    • Christoph Scholl, Rolf Drechsler, Bernd Becker
      Functional Simulation using Binary Decision Diagrams
      1997 GI/ITG/GME Workshop “Methoden des Entwurfs und der Verifikation digitaler Systeme”
    • Christoph Scholl, Rolf Drechsler, Bernd Becker
      Functional Simulation using Binary Decision Diagrams
      1997 Int'l Workshop on Logic Synth.
    • Rolf Drechsler, Bernd Becker
      Graphenbasierte Funktionsdarstellung
      B.G. Teubner, 1997
    • Nicole Göckel, Rolf Drechsler, Bernd Becker
      Learning Heuristics for OKFDD Minimization by Evolutionary Algorithms
      1997 ASP Design Automation Conf., Seiten: 469 - 472
    • C. Ökmen, Martin Keim, R. Krieger, Bernd Becker
      On Optimizing BIST Architecture by Using OBDD-based Approaches and Genetic Algorithms
      1997 VLSI Test Symp., Seiten: 426 - 431
    • Martin Keim, M. Martin, Bernd Becker, Rolf Drechsler, Paul Molitor
      Polynomial Formal Verification of Multipliers
      1997 VLSI Test Symp., Seiten: 150 - 155
    • Andreas Hett, Rolf Drechsler, Bernd Becker
      Reordering Based Synthesis
      1997 iwrm
    • Harry Hengster, Bernd Becker
      Synthesis of Fully Testable High Speed Circuits Derived from Decision Diagrams
      , 1997
    • Rolf Drechsler, Harry Hengster, H. Schäfer, J. Hartmann, Bernd Becker
      Testability of 2-Level AND/EXOR Expressions
      1997 European Design and Test Conf., Seiten: 548 - 553

    1996

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    • Rolf Drechsler, Bernd Becker, Nicole Göckel
      A Genetic Algorithm for the Construction of Small and Highly Testable OKFDD Circuits
      1996 Genetic Programming Conf., Seiten: 473 - 478
    • Nicole Göckel, G. Pudelko, Rolf Drechsler, Bernd Becker
      A Hybrid Genetic Algorithm for the Channel Routing Problem
      1996 IEEE Int'l Symp. on Circuits and Systems, Seiten: IV:675 - IV:678
    • Rolf Drechsler, Andreas Hett, Bernd Becker
      A Note on Symbolic Simulation using Desicion Diagrams
      1996 ulsi
    • Harry Hengster, Rolf Drechsler, S. Eckrich, T. Pfeiffer, Bernd Becker
      AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth
      1996 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Harry Hengster, Rolf Drechsler, S. Eckrich, T. Pfeiffer, Bernd Becker
      AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth
      1996 IEEE Asian Test Symp., Seiten: 148 - 154
    • Bernd Becker, Rolf Drechsler
      Exact Minimization of Kronecker Expressions for Symmetric Functions
      1996 IEEE Int'l Symp. on Circuits and Systems, Seiten: IV:388 - IV:391
    • Rolf Drechsler, H. Esbensen, Bernd Becker
      Genetic Algorithms in Computer Aided Design of Integrated Circuits
      1996 Online Workshop on Evolutionary Computation
    • Rolf Drechsler, Nicole Göckel, Bernd Becker
      Learning Heuristics for OBDD Minimization by Evolutionary Algorithms
      1996 Parallel Problem Solving from Nature, Springer Verlag, Band: 1141, Seiten: 730 - 739
    • Harry Hengster, U. Sparmann, Bernd Becker, Sudhakar M. Reddy
      Local Transformations and Robust Dependent Path Delay Faults
      1996 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Harry Hengster, U. Sparmann, Bernd Becker, Sudhakar M. Reddy
      Local Transformations and Robust Dependent Path Delay Faults
      1996 European Test Workshop
    • Harry Hengster, U. Sparmann, Bernd Becker, Sudhakar M. Reddy
      Local Transformations and Robust Dependent Path Delay Faults
      1996 Int'l Test Conf.
    • Andreas Hett, Rolf Drechsler, Bernd Becker
      MORE Optimization Techniques.
      , 1996
    • Rolf Drechsler, Bernd Becker
      OKFDDs - Algorithms, Applications and Extensions
      Kluwer Academic Publisher, Seiten: 163 - 190, 1996
    • Bernd Becker, Rolf Drechsler, Reinhard Enders
      On the Computational Power of Bit-Level and Word-Level Decision Diagrams
      1996 GI/ITG/GME Workshop “Methoden des Entwurfs und der Verifikation digitaler Systeme”
    • Rolf Drechsler, Harry Hengster, H. Schäfer, Bernd Becker
      Testability of AND/EXOR Expressions
      1996 European Test Workshop
    • Andreas Hett, Rolf Drechsler, Bernd Becker
      The DD Package PUMA - An Online Documentation
      https://ira.informatik.uni-freiburg.de/software/puma/, 1996

    1995

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    • Rolf Drechsler, Bernd Becker, Nicole Göckel
      A Genetic Algorithm for 2-Level AND/EXOR Minimization
      1995 SASIMI, Seiten: 49 - 56
    • Rolf Drechsler, Bernd Becker, Nicole Göckel
      A Genetic Algorithm for Variable Ordering of OBDDs
      1995 Int'l Workshop on Logic Synth., Seiten: 5c:5.55 - 5.64
    • Rolf Drechsler, Bernd Becker, Nicole Göckel
      A Genetic Algorithm for Variable Ordering of OBDDs
      , Nummer: 5/95, 1995
    • Harry Hengster, Rolf Drechsler, Bernd Becker
      AND/OR/EXOR based Synthesis of KFDD-Circuits with Small Depth
      1995 Reed-Muller Colloquium UK
    • Bernd Becker, Randal Bryant, Olivier Coudert, Christoph Meinel
      Computer Aided Design and Test, Dagstuhl-Seminar-Report 105 (9507), 13.2.1995 - 17.2.1995
      1995 Saarbrücken: Geschäftsstelle Schloss Dagstuhl
    • Rolf Drechsler, Bernd Becker, S. Ruppertz
      Dynamic Minimization of K*BMDs
      , 1995
    • Rolf Drechsler, Bernd Becker
      Dynamic Minimization of OKFDDs
      , Nummer: 5/95, 1995
    • Bernd Becker, Rolf Drechsler
      Exact Minimization of Kronecker Expressions for Symmetric Functions
      1995 IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Seiten: 240 - 245
    • R. Krieger, Bernd Becker, R. Sinković
      Necessary Assignments for an Accelerated OBDD-based Computation of Exact Fault Detection Probabilities
      1995 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • R. Krieger, Bernd Becker, C. Ökmen
      OBDD-based Optimization of Input probabilities for weighted random test
      1995 Int'l Symp. on Defect and Fault Tolerance, Seiten: 120 - 129
    • Bernd Becker, Rolf Drechsler, M. Theobald
      OKFDDs versus OBDDs and OFDDs
      1995 ICALP, Springer Verlag, Band: 944, Seiten: 475 - 486
    • Bernd Becker, Rolf Drechsler, Reinhard Enders
      On the Computational Power of Bit-Level and Word-Level Decision Diagrams
      , 1995
    • Bernd Becker, Rolf Drechsler, R. Werchner
      On the Relation Between BDDs and FDDs
      1995 Information and Computation, Band: 123(2), Seiten: 185 - 197
    • Rolf Drechsler, Bernd Becker
      PUMA: An OKFDD-Package and its Implementation
      1995 European Design and Test Conf.
    • R. Krieger, Bernd Becker, Martin Keim
      Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy
      1995 IEEE Design Automation Conference, Seiten: 339 - 344
    • Bernd Becker, Rolf Drechsler
      Synthesis for Testability: Circuits Derived from Ordered Kronecker Functional Decision Diagrams
      1995 European Design and Test Conf., Seite: 592

    1994

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    • Rolf Drechsler, M. Theobald, Bernd Becker
      Fast FDD based Minimization of Generalized Reed-Muller Forms
      1994 Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen
    • Rolf Drechsler, H. Esbensen, Bernd Becker
      Genetic Algorithms in Computer Aided Design of Integrated Circuits
      , Nummer: 17/94, 1994
    • Bernd Becker, Rolf Drechsler, M. Theobald
      Minimization of 2-level AND/XOR Expressions using Ordered Kronecker Functional Decision Diagrams
      , Nummer: 3/94, 1994
    • Rolf Drechsler, Bernd Becker, A. Jahnke
      On Variable Ordering and Decomposition Type Choice in OKFDDs
      1994 Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen
    • Rolf Drechsler, Bernd Becker, A. Jahnke
      On Variable Ordering and Decomposition Type Choice in OKFDDs
      , Nummer: 11/94, 1994
    • Bernd Becker, Rolf Drechsler, M. Theobald
      On Variable Ordering of Functional Decision Diagrams
      , Nummer: TR-94-006, 1994
    • Bernd Becker, Rolf Drechsler, M. Theobald
      On Variable Ordering of Ordered Functional Decision Diagrams
      1994 GI/GME/ITG-Fachtagung “Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme”, Springer Verlag, Seiten: 62 - 71
    • Rolf Drechsler, A. Sarabi, M. Theobald, Bernd Becker, M. A. Perkowski
      On the Computational Power of Ordered Kronecker Functional Decision Diagrams
      , Nummer: 4/94, 1994
    • Rolf Drechsler, A. Sarabi, M. Theobald, Bernd Becker, M. A. Perkowski
      Ordered Kronecker Functional Decision Diagrams: An Efficient Tool for Synthesis and Verification
      1994 GI/ITG Workshop “Anwendung formaler Methoden im Systementwurf”
    • Bernd Becker, Rolf Drechsler
      Synthesis for Testability: Circuits Derived from Ordered Kronecker Functional Decision Diagrams
      1994 Int'l Test Synthesis Workshop
    • Bernd Becker, Rolf Drechsler
      Synthesis for Testability: Circuits Derived from Ordered Kronecker Functional Decision Diagrams
      , Nummer: 14/94, 1994
    • Harry Hengster, Rolf Drechsler, Bernd Becker
      Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model
      1994 Int'l Conf. on VLSI Design, Seiten: 123 - 126
    • Bernd Becker, Rolf Drechsler
      Testability of Circuits Derived from Functional Decision Diagrams
      1994 European Design and Test Conf., Seite: 667

    1993

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    • Bernd Becker, Rolf Drechsler, Harry Hengster, R. Krieger, R. Sinković
      Binary Decision Diagrams and Testing
      1993 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Bernd Becker, Randal Bryant, Christoph Meinel
      Computer Aided Design and Test: 15.2.1993-19.2.1993 (9307), Dagstuhl Seminar Report 56
      1993 Saarbrücken: Geschäftsstelle Schloss Dagstuhl
    • Rolf Drechsler, A. Sarabi, M. Theobald, Bernd Becker, M. A. Perkowski
      Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams
      , Nummer: 14/93, 1993
    • Rolf Drechsler, M. Theobald, Bernd Becker
      Fast FDD based Minimization of Generalized Reed-Muller Forms
      , Nummer: 15/93, 1993
    • Bernd Becker, Rolf Drechsler, Harry Hengster
      Local Circuit Transformations Preserving Robust Path-Delay-Fault Testability
      , Nummer: 1/93, 1993
    • Bernd Becker, Rolf Drechsler, Paul Molitor
      On Generation of Area-Time Optimal Testable Adders
      1993 Technical Report 3/93
    • Bernd Becker, Rolf Drechsler, M. Theobald
      On Variable Ordering of Functional Decision Diagrams
      , 1993
    • Bernd Becker, Rolf Drechsler
      On the Computational Power of Functional Decision Diagrams
      1993 Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen
    • Bernd Becker, Rolf Drechsler, M. Theobald
      On the Implementation of a Package for Efficient Representation and Manipulation of Functional Decision Diagrams
      1993 IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Seiten: 162 - 169
    • Bernd Becker, Rolf Drechsler, R. Werchner
      On the Relation between BDDs and FDDs
      , Nummer: 12/93, 1993
    • Bernd Becker, Rolf Drechsler, Christoph Meinel
      On the Testability of Circuits Derived from Binary Decision Diagrams
      , Nummer: 9/93, 1993
    • Rolf Drechsler, Bernd Becker
      Rapid Prototyping of Fully Testable Multi-Level AND/EXOR Networks
      1993 IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Seiten: 126 - 133
    • Bernd Becker, Rolf Drechsler
      Testability of Circuits Derived from Functional Decision Diagrams
      , 1993
    • Ralf Hahn, Bernd Becker, Harry Hengster
      The Fault Graph and its Application to Combinational Fault Simulation
      1993 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • R. Krieger, Bernd Becker, Harry Hengster
      lgc++: Ein Werkzeug zur Implementierung von Logiken als abstrakte Datentypen in C++
      , 1993
    • R. Krieger, Ralf Hahn, Bernd Becker
      test_circ: Ein abstrakter Datentyp zur Repräsentation von hierarchischen Schaltkreisen
      , 1993

    1992

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    • Rolf Drechsler, Bernd Becker, Paul Molitor
      A Performance Oriented Generator for Robust Path-Delay-Fault Testable Adders
      1992 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Bernd Becker, Rolf Drechsler, Paul Molitor
      On the Implementation of an Efficient Performance Driven Generator for Conditional-Sum-Adders.
      1992 Technical Report 2/93
    • Rolf Drechsler, Bernd Becker
      Rapid Prototyping of Robust Path-Delay-Fault Testable Circuits Derived from Binary Decision Diagrams
      , Nummer: TR-17/92, SFB 124, 1992

    1991

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    • Bernd Becker, Christoph Meinel
      Entwerfen, Prüfen, Testen: 18.2.1991-22.2.1991 (9108), Dagstuhl-Seminar-Report 6
      1991 Saarbrücken: Geschäftsstelle Schloss Dagstuhl

    1988

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    • Bernd Becker, U. Sparmann
      A Uniform Test Approach for RCC-Adders
      1988 Aegean Workshop on Parallel Computation and VLSI Theory, Springer Verlag, Band: 319, Seiten: 288 - 300

    1987

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    • Bernd Becker
      An Easily Testable Optimal-Time VLSI-Multiplier
      1987 Acta Informatica, Band: 24, Seiten: 363 - 380
    • Bernd Becker, G. Hotz, R. Kolla, Paul Molitor, H. G. Osthof
      CADIC - Ein System zum hierarchischen Entwurf integrierter Schaltungen
      1987 E.I.S.-Workshop, Seiten: 235 - 245
    • Bernd Becker, H. G. Osthof
      Layouts with Wires of Balanced Length
      1987 Information and Computation, Band: 73(1), Seiten: 45 - 58

    1986

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    • Bernd Becker, G. Hotz, R. Kolla, Paul Molitor
      Ein logisch-topologischer Kalkül zur Konstruktion von integrierten Schaltkreisen
      1986 INFORMATIK Forschung und Entwicklung 1, Seite: 38--47,72-

    1983

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    • Bernd Becker
      On the Crossing-free, Rectangular Embedding of Weighted Graphs in the Plane
      1983 Theor. Comput. Sci., GI-Conf., Springer Verlag, Band: 145, Seiten: 61 - 72