RealTest I — erste Förderperiode (abgeschlossen)

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In the RealTest project, we work on systems whose behaviour cannot be specified by well-defined, deterministic values, as traditionally usual, but by a range of values that can be accepted depending on the application conditions. For instance, a video-chip that occasionally computes wrong values for only few pixels can still find an application. In the current practice, such a chip would be thrown away, although it could be sold for a reduced price to be used in applications that would tolerate such behaviour. For example, in consumer electronics (TV sets, mobile phones, etc), such errors would usually remain unnoticed by the human eye, or they would become irrelevant when taking into consideration that broadcast signals are noisy anyway. Obviously, using such “second-class” chips instead of throwing them away consitutes an economic advantage for the manufacturer.

The focus of our research lies in methods for specification, test and verification of circuits with so-called acceptable behaviour. We consider timing and data issues, as well as hard (permanent) and transient faults. In a joint work with Prof. John P. Hayes from the University of Michigan, we developed the concept of transient-error tolerance in order to reflect the acceptance of timing anomalies. Here, a circuit is allowed to produce wrong outputs for a certain number of clock cycles after the occurrence of a soft error, as long as a certain probability for the circuit being able to return to its normal behaviour can be guaranteed.

The analysis is based on the construction of a Markov model to grade the probability that fault effects are still visible after k cycles. The following graphs show a serial adder, its corresponding state diagram, the Markov model and the error probability in terms of k.

Furthermore, we developed a selective-hardening method that can be used to harden only specific parts of a circuit, such as to reduce the cost of making a circuit comply with its transient-error-tolerant specifications, i.e. to be able to return to normal behaviour after at most k clock cycles with a guaranteed probability. The following diagram shows for an example benchmark circuit (ISCAS 89’s s298) the cost of the selective-hardening approach depending on various k-values and various error probabilities. A cost of 100 represents tha hardening of 100% of the circuit components.

The following graph illustrates the aim of our research approach. Transient-error tolerance can be combined with methods that grade the application-specific acceptability of errors. The metric d represents the gap between the observed behaviour and the reference behaviour. The behaviour is acceptable if that gap is not too large, i.e. as long as the observed behaviour lies withing the τ-tube, and the circuit returns to the reference behaviour after at most k clock cycles. We work on psycho-visual metrics for imaging applications.

conference and journal papers (refereed)

• I. Polian, B. Becker, M. Nakasato, S. Ohtake and H. Fujiwara, “Low-Cost Hardening of Image Processing Applications Against Soft Errors,” in Int’l Symp. on Defect and Fault Tolerance, pp. 274–279, 2006.


• I. Polian, S.M. Reddy, I. Pomeranz, X. Tang and B. Becker, “On Reducing Circuit Malfunctions Caused by Soft Errors,” in Int’l Symp. on Defect and Fault Tolerance, pp. 245–253, 2008.


• D. Nowroth, I. Polian and B. Becker, “A Study of Cognitive Resilience in a JPEG Compressor,” in Int’l Conf. on Dependable Systems and Networks, pp. 32–41, 2008.


• C.G. Zoellin, H.-J.Wunderlich, I. Polian and B. Becker, “Selective Hardening in Early Design Steps,” in European Test Symp., pp. 185–190, 2008.


• S. Kundu and I. Polian, “An Improved Technique for Reducing False Alarms Due to Soft Errors,” in Int’l On-Line Test Symp., pp. 105–110, 2006.


• I. Polian, D. Nowroth and B. Becker, “Identification of Critical Errors in Imaging Applications,” in Int’l On-Line Test Symp., pp. 201–202, 2007. (Poster).


• I. Polian, S.M. Reddy and B. Becker, “Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors,” in IEEE Int’l Symp. on VLSI, pp. 257–262, 2008.


• J.P. Hayes, I. Polian and B. Becker, “An Analysis Framework for Transient-Error Tolerance,” in VLSI Test Symp., pp. 249–255, 2007.


• I. Polian, J.P. Hayes, D. Nowroth and B. Becker, “Ein kostenbegrenzter Ansatz zur Reduktion der transienten Fehlerrate,” in GMM/GI/ITG Reliability and Design Conf., pp. 183–184, 2007. (Poster).

conference and journal papers (invited)

• B. Becker, I. Polian, S. Hellebrand, B. Straube and H.-J.Wunderlich, “DFGProjekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFGProject - Test and Reliability of Nano-Electronic Systems),” it - Information Technology, vol. 48, no. 5, p. 304, 2006.


• B. Becker, I. Polian, S.Hellebrand, B. Straube and H.-J.Wunderlich, “Test und Zuverlässigkeit Nanoelektronischer Systeme,” in GMM/GI/ITG Reliability and Design Conf., pp. 139–140, 2007.

workshop papers

• J.P. Hayes, I. Polian and B. Becker, “A Model for Transient Faults in Logic Circuits,” in Int’l Design and TestWorkshop, 2006.


• I. Polian, B. Becker, M.Nakasato, S.Ohtake and H. Fujiwara, “Period of Grace: A New Paradigm for Efficient Soft Error Hardening,” in GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, 2006.


• I. Polian, S.M. Reddy, I. Pomeranz, X. Tang and B. Becker, “No Free Lunch in Error Protection?,” in Workshop on Dependable and Secure Nanocomputing, 2008.


• I. Polian, J.P. Hayes and B. Becker, “Cost-Ecient Circuit Hardening Based on Critical Soft Error Rate,” in IEEEWorkshop on RTL ATPG and DfT, 2007.