2020

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• Tobias Paxian, Mael Gay, Devanshi Upadhyaya, Bernd Becker, Ilia Polian
  SAT Benchmarks of AutoFault Attacking AES, LED and PRESENT
  2020 SAT COMPETITION 2020, volume: 20, pages: 79 - 79

2019

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• Ilia Polian, Mael Gay, Tobias Paxian, Sauer Matthias, Bernd Becker
  Automatic construction of fault attacks on cryptographic hardware implementations
  2019 Automated Methods in Cryptographic Fault Analysis, volume: 1, pages: 151 - 170
• Mael Gay, Tobias Paxian, Devanshi Upadhyaya, Bernd Becker, Ilia Polian
  Hardware-oriented algebraic fault attack framework with multiple fault injection support
  2019 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), volume: 16, pages: 25 - 32
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  Abstract

  The evaluation of fault attacks on security-critical hardware implementations of cryptographic primitives is an important concern. In such regards, we have created a framework for automated construction of fault attacks on hardware realization of ciphers. The framework can be used to quickly evaluate any cipher implementations, including any optimisations. It takes the circuit description of the cipher and the fault model as input. The output of the framework is a set of algebraic equations, such as conjunctive normal form (CNF) clauses, which is then fed to a SAT solver. We consider both attacking an actual implementation of a cipher on an field-programmable gate array (FPGA) platform using a fault injector and the evaluation of an early design of the cipher using idealized fault models. We report the successful application of our hardware-oriented framework to a collection of ciphers, including the advanced encryption standard (AES), and the lightweight block ciphers LED and PRESENT. The corresponding results and a discussion of the impact to different fault models on our framework are shown. Moreover, we report significant improvements compared to similar frameworks, such as speedups or more advanced features. Our framework is the first algebraic fault attack (AFA) tool to evaluate the state-of-the art cipher LED-64, PRESENT and full-scale AES using only hardware-oriented structural cipher descriptions.

2017

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• Jan Burchard, Maël Gay, Ange-Salomé Messeng Ekossono, Jan Horáček, Bernd Becker, Tobias Schubert, Martin Kreuzer, Ilia Polian
  Attacks
  2017 Fault Diagnosis and Tolerance in Cryptography (FDTC) 2017
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  Abstract

  A prototype of the framework AutoFault, which automatically constructs fault-injection attacks for hardware realizations of ciphers, is presented. AutoFault can be used to quickly evaluate the resistance of security-critical hardware blocks to fault attacks and the adequacy of implemented countermeasures. The framework takes as inputs solely the circuit description of the cipher and the fault(s) and produces an algebraic formula that can be handed over to an external solver. In contrast to previous work, attacks constructed by AutoFault do not incorporate any cipher-specific cryptoanalytic derivations, making the framework accessible to users without cryptographic background. We report successful application of AutoFault in combination with a state-of-the-art SAT solver to LED-64 and to small-scale AES. To the best of our knowledge, this is the first time that a state-of-the-art cipher (LED-64) was broken by a fault attack with no prior manual cryptanalysis whatsoever.
• Matthias Sauer, Pascal Raiola, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian
  Sensitized Path PUF: A Lightweight Embedded Physical Unclonable Function
  2017 Conf. on Design, Automation and Test in Europe
• Jan Burchard, Ange-Salomé Messeng Ekossono, Jan Horáček, Maël Gay, Bernd Becker, Tobias Schubert, Martin Kreuzer, Ilia Polian
  Algebraic Fault Attacks on Ciphers
  2017 RESCUE Workshop on Reliability, Security and Quality at ETS 2017
• Jan Burchard, Ange-Salomé Messeng Ekossono, Jan Horáček, Maël Gay, Bernd Becker, Tobias Schubert, Martin Kreuzer, Ilia Polian
  Algebraic Fault Attacks on Ciphers
  2017 International Verification and Security Workshop (IVSW) 2017

2016

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• Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian
  On Optimal Power-aware Path Sensitization
  2016 2016 25nd IEEE Asian Test Symposium (ATS)
• Maël Gay, Jan Burchard, Jan Horáček, Ange-Salomé Messeng Ekossono, Tobias Schubert, Bernd Becker, Ilia Polian, Martin Kreuzer
  Formulas, Circuit-Implementations and Fault Equations
  2016 FCTRU'16
• Matthias Sauer, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian
  Utilizing Intrinsic Delay Variability in Complex Digital Circuits for Defining PUF Behavior
  2016 TRUDEVICE Workshop, Dresden

2015

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• Linus Feiten, Matthias Sauer, Tobias Schubert, Victor Tomashevich, Ilia Polian, Bernd Becker
  Formal Vulnerability Analysis of Security Components
  2015 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume: 34, issue: 8, pages: 1358 - 1369
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  Abstract

  Vulnerability to malicious fault attacks is an emerging concern for hardware circuits that are employed in mobile and embedded systems and process sensitive data. We describe a new methodology to assess the vulnerability of a circuit to such attacks, taking into account built-in protection mechanisms. Our method is based on accurate modeling of fault effects and detection status expressed by Boolean satisfiability (SAT) formulas. Vulnerability is quantified based on the number of solutions of these formulas, which are determined by an efficient #SAT solver. We demonstrate the applicability of this method for design space exploration of a pseudo random number generator and for calculating the attack success rate in a multiplier circuit protected by robust error-detecting codes.
• Matthias Sauer, Bernd Becker, Ilia Polian
  PHAETON: A SAT-based Framework for Timing-aware Path Sensitization
  2015 Ieee T Comput, volume: PP, issue: 99
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  Abstract

  nowledge about sensitizable paths through combinational logic is essential for numerous design tasks. We present the framework PHAETON which identifies sensitizable paths and generates test pairs to exercise these paths using Boolean satisfiability (SAT). PHAETON supports a large number of models and sensitization conditions and provides a generic interface that can be used by applications. It incorporates a novel application-specific unary representation of integer numbers to integrate timing information with logical conditions within the same monolithic SAT formula. Due to a number of further elaborate speedup techniques, PHAETON scales to industrial circuits. Experimental results show the performance of PHAETON in classical K longest path generation tasks and in new post-silicon validation and characterization scenarios.

2014

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• Matthias Sauer, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker
  Variation-Aware Deterministic ATPG
  2014 IEEE European Test Symposium , pages: 1 - 6
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  Abstract

  In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability. As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level. The algorithm combines a classical path-oriented test-generation procedure with a novel waveformaccurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency. Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations.

2013

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• Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Victor Tomashevich, Eberhard Böhl, Ilia Polian, Bernd Becker
  #SAT for Vulnerability Analysis of Security Components
  2013 (Workshop-Paper, Informal Proceedings) IEEE European Test Symposium
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  Abstract

  Vulnerability to malicious fault attacks is an emerging concern for hardware circuits that process sensitive data.We describe a new methodology to assess the vulnerability to such attacks, taking into account built-in protection mechanisms. Our method is based on accurate modeling of fault effects and their detection status expressed as Boolean satisfiability (SAT) formulae. Vulnerability is quantified based on the number of solutions of such formulae, which are computed by an eficient #SAT solver. We demonstrate the applicability of this method by analyzing a sequential pseudo random number generator and a combinatorial multiplier circuit both protected by robust error-detecting codes.
• Matthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker
  Efficient SAT-Based Dynamic Compaction and Relaxation for Longest Sensitizable Paths
  2013 Conf. on Design, Automation and Test in Europe, pages: 448 - 453
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  Abstract

  Comprehensive coverage of small-delay faults under massive process variations is achieved when multiple paths through the fault locations are sensitized by the test pair set. Using one test pair per path may lead to impractical test set sizes and test application times due to the large number of near-critical paths in state-of-the-art circuits.
• Matthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker
  Provably Optimal Test Cube Generation Using Quantified Boolean Formula Solving
  2013 ASP Design Automation Conf.
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  Abstract

  Circuits that employ test pattern compression rely on test cubes to achieve high compression ratios. The less inputs of a test pattern are specified, the better it can be compacted and hence the lower the test application time. Although there exist previous approaches to generate such test cubes, none of them are optimal. We present for the first time a framework that yields provably optimal test cubes by using the theory of quantified Boolean formulas (QBF). Extensive comparisons with previous methods demonstrate the quality gain of the proposed method.
• Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker
  SAT-based Analysis of Sensitisable Paths
  2013 Test of Computers, volume: 30, issue: 4, pages: 81 - 88
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  Abstract

  A common trend in the past has been to detect delay defects in nanoscale technologies through the longest sensitisable paths. This approach does not hold up for non-trivial defects due to modeling inaccuracies. This article supports tests through all paths of customized length, using current SAT-solving advances.
• Matthias Sauer, Jan Burchard, Tobias Schubert, Ilia Polian, Bernd Becker
  Waveform-Guided Fault Injection by Clock Manipulation
  2013 TRUDEVICE Workshop

2012

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• Alexander Czutro, Michael Imhof, Jie Jiang, Abdullah Mumtaz, Matthias Sauer, Bernd Becker, Ilia Polian, Hans-Joachim Wunderlich
  Variation-Aware Fault Grading
  2012 IEEE Asian Test Symp., pages: 344 - 349
• Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Eberhard Böhl, Ilia Polian, Bernd Becker
  #SAT-Based Vulnerability Analysis of Security Components -- A Case Study
  2012 IEEE International Symposium on Defect and Fault Tolerance (DFT), pages: 49 - 54
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  Abstract

  In this paper we describe a new approach to assess a circuit's vulnerability to fault attacks. This is achieved through analysis of the circuit's design specification, making use of modern SAT solving techniques. For each injectable fault, a corresponding SAT instance is generated. Every satisfying solution for such an instance is equivalent to a circuit state and an input assignment for which the fault affcts the circuit's outputs such that the error is not detected by the embedded fault detection. The number of solutions is precisely calculated by a #SAT solver and can be translated into an exact vulnerability measure. We demonstrate the applicability of this method for design space exploration by giving detailed results for various implementations of a deterministic random bit generator.
• Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
  Functional Justification in Sequential Circuits using SAT and Craig Interpolation
  2012 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
• Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
  Functional Test of Small-Delay Faults using SAT and Craig Interpolation
  2012 Int'l Test Conf., pages: 1 - 8
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  Abstract

  We present SATSEQ, a timing-aware ATPG system for small-delay faults in non-scan circuits. The tool identifies the longest paths suitable for functional fault propagation and generates the shortest possible sub-sequences per fault. Based on advanced model-checking techniques, SATSEQ provides detection of small-delay faults through the longest functional paths. All test sequences start at the circuit's initial state; therefore, overtesting is avoided. Moreover, potential invalidation of the fault detection is taken into account. Experimental results show high detection and better performance than scan testing in terms of test application time and overtesting-avoidance.
• Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker
  Multi-Conditional ATPG using SAT with Preferences
  2012 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
• Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker
  Multi-Conditional SAT-ATPG for Power-Droop Testing
  2012 IEEE European Test Symp.
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  Abstract

  Power droop is a non-trivial signal-integrity-related effect triggered by specific power-supply conditions. High-frequency and low-frequency power droop may lead to failure of an IC during application time, but they usually remain undetected by state-of-the-art manufacturing test methods, as the fault excitation imposes particular conditions on global switching activity over several time frames. Hence, ATPG for power-droop test (PD-ATPG) is an extremely hard problem that has not yet been solved optimally. In this paper, we use a SAT-based ATPG engine that employs a mechanism known as SAT-solving with qualitative preferences to generate a solution guaranteed to be optimal for a given set of optimisation criteria, however at the expense of high SAT-solving times. Therefore, a well-balanced set of criteria has to be chosen for the SAT-formulation in order to get as good solutions as possible without rendering the SAT-instances impracticably hard. We explore several strategies and evaluate them experimentally.
• Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
  On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints
  2012 Conf. on Design, Automation and Test in Europe, pages: 418 - 423
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  Abstract

  Adequate coverage of small-delay defects in circuits affected by statistical process variations requires identification and sensitization of multiple paths through potential defect sites. Existing K longest path generation (KLPG) algorithms use a data structure called path store to prune the search space by restricting the number of sub-paths considered at the same time. While this restriction speeds up the KLPG process, the algorithms lose their optimality and do not guarantee that the K longest sensitizable paths are indeed found. We investigate, for the first time, the effects of missing some of the longest paths on the defect coverage. We systematically quantify how setting different limits on the path-store size affects the numbers and relative lengths of identified paths, as well as the run-times of the algorithm. We also introduce a new optimal KLPG algorithm that works iteratively and pinpointedly addresses defect locations for which the path-store size limit has been exceeded in previous iterations. We compare this algorithm with a naïve KLPG approach that achieves optimality by setting the path-store size limit to a very large value. Extensive experiments are reported for 45nm-technology data.
• Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
  On the Quality of Test Vectors for Post-Silicon Characterization
  2012 IEEE European Test Symp.
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  Abstract

  Post-silicon validation, i.e., physical characterization of a small number of fabricated circuit instances before start of high-volume manufacturing, has become an essential step in integrated circuit production. Post-silicon validation is required to identify intricate logic or electrical bugs which could not be found during pre-silicon verification. In addition, physical characterization is useful to determine the performance distribution of the manufactured circuit instances and to derive performance yield. Test vectors used for this step are subject to different requirements compared to vectors for simulation-based verification or for manufacturing test. In particular, they must sensitize a very comprehensive set of paths in the circuit, assuming massive variations and possible modeling deficiencies. An inadequate test vector set may result in overly optimistic yield estimates and wrong manufacturing decisions. On the other hand, the size of the test vector set is less important than in verification or manufacturing test. In this paper, we systematically investigate the relationship between the quality of the employed test vectors and the accuracy of yield-performance predictions. We use a highly efficient SAT-based algorithm to generate comprehensive test vector sets based on simple model assumptions and validate these test sets using simulated circuit instances which incorporate effects of process variations. The obtained vector sets can also serve as a basis for adaptive manufacturing test.
• Alexander Czutro, Matthias Sauer, Tobias Schubert, Ilia Polian, Bernd Becker
  SAT-ATPG Using Preferences for Improved Detection of Complex Defect Mechanisms
  2012 VLSI Test Symp.
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  Abstract

  Failures caused by phenomena such as crosstalk or power-supply noise are gaining in importance in advanced nanoscale technologies. The detection of such complex defects benefits from the satisfaction of certain constraints, for instance justifying specific transitions on neighbouring lines of the defect location. We present a SAT-based ATPG-tool that supports the enhanced conditional multiple-stuck-at fault model (ECMS@). This model can specify multiple fault locations along with a set of hard conditions imposed on arbitrary lines; hard conditions must hold in order for the fault effect to become active. Additionally, optimisation constraints that may be required for best coverage can be specified via a set of soft conditions. The introduced tool justifies as many of these conditions as possible, using a mechanism known as SAT with preferences. Several applications are discussed and evaluated by extensive experimental data. Furthermore, a novel fault-clustering technique is introduced, thanks to which the time required to classify all stuck-at faults in a suite of industrial benchmarks was reduced by up to 65%.
• Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker
  Small-Delay-Fault ATPG with Waveform Accuracy
  2012 Int'l Conf. on CAD, pages: 30 - 36
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  Abstract

  The detection of small-delay faults is traditionally performed by sensitizing transitions on a path of sufficient length from an input to an output of the circuit going through the fault site. While this approach allows efficient test generation algorithms, it may result in false positives and false negatives as well, i.e. undetected faults are classified as detected or detectable faults are classified as undetectable. We present an automatic test pattern generation algorithm which considers waveforms and their propagation on each relevant line of the circuit. The model incorporates individual delays for each gate and filtering of small glitches. The algorithm is based on an optimized encoding of the test generation problem by a Boolean satisfiability (SAT) instance and is implemented in the tool WaveSAT. Experimental results for ISCAS-85, ITC-99 and industrial circuits show that no known definition of path sensitization can eliminate false positives and false negatives at the same time, thus resulting in inadequate small-delay fault detection. WaveSAT generates a test if the fault is testable and is also capable of automatically generating a formal redundancy proof for undetectable small-delay faults; to the best of our knowledge this is the first such algorithm that is both scalable and complete.

2011

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• Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
  On the Optimality of K Longest Path Generation
  2011 Workshop on RTL and High Level Testing
• Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker
  Estimation of Component Criticality in Early Design Steps
  2011 IEEE Int'l Online Testing Symp., pages: 104 - 110
• Matthias Sauer, Victor Tomashevich, Jörg Müller, Matthew Lewis, Ilia Polian, Bernd Becker, Wolfram Burgard
  An FPGA-Based Framework for Run-time Injection and Analysis of Soft Errors in Microprocessors
  2011 IEEE Int'l Online Testing Symp., pages: 182 - 185
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  Abstract

  State-of-the-art cyber-physical systems are increasingly deployed in harsh environments with non-negligible soft error rates, such as aviation or search-and-rescue missions. State-of-the-art nanoscale manufacturing technologies are more vulnerable to soft errors. In this paper, we present an FPGA-based framework for injecting soft errors into user-specified memory elements of an entire microprocessor (MIPS32) running application software. While the framework is applicable to arbitrary software, we demonstrate its usage by characterizing soft errors effects on several software filters used in aviation for probabilistic sensor data fusion.
• Matthias Sauer, Jie Jiang, Alexander Czutro, Ilia Polian, Bernd Becker
  Efficient SAT-Based Search for Longest Sensitisable Paths
  2011 Test Symposium (ATS), 2011 20th Asian, pages: 108 - 113
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  Abstract

  We present a versatile method that enumerates all or a user-specified number of longest sensitisable paths in the whole circuit or through specific components. The path information can be used for design and test of circuits affected by statistical process variations. The algorithm encodes all aspects of the path search as an instance of the Boolean Satisfiability Problem (SAT), which allows the method not only to benefit from recent advances in SAT-solving technology, but also to avoid some of the drawbacks of previous structural approaches. Experimental results for academic and industrial benchmark circuits demonstrate the method's accuracy and scalability.
• Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker
  SAT-Based Analysis of Sensitisable Paths
  2011 IEEE Design and Diagnostics of Electronic Circuits and Systems, pages: 93 - 98
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  Abstract

  Manufacturing defects in nanoscale technologies have highly complex timing behaviour that is also affected by process variations. While conventional wisdom suggests that it is optimal to detect a delay defect through the longest sensitisable path, non-trivial defect behaviour along with modelling inaccuracies necessitate consideration of paths of well-controlled length during test generation. We present a generic methodology that yields tests through all sensitisable paths of user-specified length. The resulting tests can be employed within the framework of adaptive testing. The methodology is based on encoding the problem as a Boolean-satisfiability (SAT) instance and thereby leverages recent advances in SAT-solving technology.

2010

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• Ilia Polian, Bernd Becker
  Fault Models and Test Algorithms for Nanoscale Technologies
  2010 it - Information Technology, volume: 52, issue: 4, pages: 189 - 194
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  Abstract

  In the age of Nanoscale Integration (NSI), state-of-the-art integrated circuits with gate length under 100 nm consist of hundreds of millions of transistors. This implies new challenges for their reliability. Novel NSI defect mechanisms require special test methods to sort out faulty chips. We present modeling approaches and efficient test algorithms for fundamental NSI defect mechanisms enabling the handling of industrial multi-million-gate circuits.
• Alexander Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
  Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis
  2010 International Journal of Parallel Programming, volume: 38, issue: 3-4, pages: 185 - 202
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  Abstract

  Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.
• Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich
  Variation-Aware Fault Modeling
  2010 IEEE Asian Test Symp., pages: 87 - 93
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  Abstract

  To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simu-lations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defect-induced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45nm technology.

2009

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• Alexander Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
  Dynamic Compaction in SAT-Based ATPG
  2009 IEEE Asian Test Symp.
• Alexander Czutro, Bernd Becker, Ilia Polian
  Performance Evaluation of SAT-Based ATPG on Multi-Core Architectures
  2009 Test Symposium
• Marc Hunger, Sybille Hellebrand, Alexander Czutro, Ilia Polian, Bernd Becker
  Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung
  2009 GMM/ITG-Fachtagung “Zuverlässigkeit und Entwurf”
• Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian
  SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges
  2009 ACM Trans. on Design Automation of Electronic Systems, volume: 14, issue: 4, pages: 56:1 - 56:21
• Marc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, Bernd Becker
  ATPG-Based Grading of Strong Fault-Secureness
  2009 IEEE Int'l Online Testing Symp.
• Nicolas Houarche, Alejandro Czutro, Mariane Comte, Piet Engelke, Ilia Polian, Bernd Becker, Michel Renovell
  An Electrical Model for the Fault Simulation of Small-Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects
  2009 VLSI Test Symp.
• Nicolas Houarche, Alejandro Czutro, Mariane Comte, Piet Engelke, Ilia Polian, Bernd Becker, Michel Renovell
  Deriving an Electrical Model for Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects
  2009 Latin-American Test Workshop
• Alejandro Czutro, Bernd Becker, Ilia Polian
  Performance Evaluation of SAT-Based Automatic Test Pattern Generation on Multi-Core Architectures
  2009 GI/ITG Int'l Conf. on Architecture of Computing Systems, Many-Cores Workshop
• Alejandro Czutro, Bernd Becker, Ilia Polian
  Performance Evaluation of SAT-Based ATPG on Multi-Core Architectures
  2009 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
• Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
  TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis
  2009 Int'l Conf. on VLSI Design, pages: 227 - 232
• V. Izosimov, Ilia Polian, P. Pop, P. Eles, Z. Peng
  Analysis and optimization of fault-tolerant embedded systems with hardened processors
  2009 Conf. on Design, Automation and Test in Europe
• Stefan Hillebrecht, Ilia Polian, P. Ruther, S. Herwik, Bernd Becker, Oliver Paul
  Reliability Characterization of Interconnects in CMOS Integrated Circuits Under Mechanical Stress
  2009 Int'l Reliability Physics Symp.

2008

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• Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker
  A Simulator of Small-Delay Faults Caused by Resistive-Open Defects
  2008 IEEE European Test Symp., pages: 113 - 118
• Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
  TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis
  2008 edaWorkshop
• Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker
  On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
  2008 IEEE Trans. on CAD, volume: 27, issue: 2, pages: 327 - 338
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  Abstract

  Test application at reduced power supply voltage (low-voltage testing) or reduced temperature (low-temperature testing) can improve the defect coverage of a test set, in particular of resistive short defects. Using a probabilistic model of these defects, we quantify the coverage impact of low-voltage and low-temperature testing for different voltages and temperatures. When considering the coverage increase, we differentiate between defects missed by the test set at nominal conditions and undetectable defects (flaws) detected at non-nominal conditions. In our analysis, the performance degradation of the device caused by lower power supply voltage is accounted for. Furthermore, we describe a situation in which defects detected by conventional testing are missed by low-voltage testing and quantify the resulting coverage loss. Experimental results suggest that test quality is improved even if no cost increase is allowed. If multiple test applications are acceptable, a combination of low-voltage and low-temperature turns out to provide the best coverage of both hard defects and flaws.
• Damian Nowroth, Ilia Polian, Bernd Becker
  A Study of Cognitive Resilience in a JPEG Compressor
  2008 Int'l Conf. on Dependable Systems and Networks, pages: 32 - 41
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  Abstract

  Many classes of applications are inherently tolerant to errors. One such class are applications designed for a human end user, where the capabilities of the human cognitive system (cognitive resilience) may compensate some of the errors produced by the application. We present a methodology to automatically distinguish between tolerable errors in imaging applications which can be handled by the human cognitive system and severe errors which are perceptible to a human end user. We also introduce an approach to identify non-critical spots in a hardware circuit which should not be hardened against soft errors because errors that occur on these spots are tolerable. We demonstrate that over 50% of flip-flops in a JPEG compressor chip are non-critical and require no hardening.
• Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
  Automatic Test Pattern Generation for Interconnect Open Defects
  2008 VLSI Test Symp., pages: 181 - 186
• Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
  Automatic Test Pattern Generation for Interconnect Open Defects
  2008 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
• Ilia Polian, Yusuke Nakamura, Piet Engelke, Stefan Hillebrecht, Kohei Miyase, Seiji Kajihara, Bernd Becker, Xiaoqing Wen
  Diagnose realistischer Defekte mit Hilfe des X-Fehlermodells
  2008 GMM/GI/ITG Reliability and Design Conf., pages: 155 - 156
• Ilia Polian, Yusuke Nakamura, Piet Engelke, Stefan Spinner, Kohei Miyase, Seiji Kajihara, Bernd Becker, Xiaoqing Wen
  Diagnosis of Realistic Defects Based on the X-Fault Model
  2008 IEEE Design and Diagnostics of Electronic Circuits and Systems, pages: 263 - 268
• Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
  Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model
  2008 Int'l Test Conf., pages: 1 - 10
• Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, X. Tang, Bernd Becker
  No Free Lunch in Error Protection?
  2008 Workshop on Dependable and Secure Nanocomputing
• Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, X. Tang, Bernd Becker
  On Reducing Circuit Malfunctions Caused by Soft Errors
  2008 Int'l Symp. on Defect and Fault Tolerance, pages: 245 - 253
• Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker
  Resistive Bridging Fault Simulation of Industrial Circuits
  2008 Conf. on Design, Automation and Test in Europe, pages: 628 - 633
  » show abstract« hide abstract
  Abstract

  We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophisticated RBF model, the run times of the simulator were within an order of magnitude of the run times for pattern-parallel complete-circuit stuck-at fault simulation. Industrial-size circuits, including a multi-million-gates design, could be simulated in reasonable time despite a significantly higher number of faults to be simulated compared with stuck-at fault simulation.
• Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker
  Resistive Bridging Fault Simulation of Industrial Circuits
  2008 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
• Ilia Polian, Sudhakar M. Reddy, Bernd Becker
  Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors
  2008 IEEE Int'l Symp. on VLSI, pages: 257 - 262
• Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker
  Selective Hardening in Early Design Steps
  2008 IEEE European Test Symp., pages: 185 - 190
• Ilia Polian, W. Rao
  Selective Hardening of NanoPLA Circuits
  2008 Int'l Symp. on Defect and Fault Tolerance, pages: 263 - 271

2007

 back to the year overview

• Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
  Power Droop Testing
  2007 Test of Computers, volume: 24, issue: 3, pages: 276 - 284
• Stefan Spinner, Ilia Polian, Bernd Becker, P. Ruther, Oliver Paul
  A System for the Calibration and Reliability Testing of MEMS Devices Under Mechanical Stress
  2007 VDE Microsystem Technology Congress, pages: 861 - 864
• John P. Hayes, Ilia Polian, Bernd Becker
  An Analysis Framework for Transient-Error Tolerance
  2007 VLSI Test Symp., pages: 249 - 255
• Ilia Polian, John P. Hayes, Bernd Becker
  Cost-Efficient Circuit Hardening Based on Critical Soft Error Rate
  2007 IEEE Workshop on RTL ATPG and DfT
• Ilia Polian, John P. Hayes, Damian Nowroth, Bernd Becker
  Ein kostenbegrenzter Ansatz zur Reduktion der transienten Fehlerrate
  2007 GMM/GI/ITG Reliability and Design Conf., pages: 183 - 184
• Ilia Polian, Hideo Fujiwara
  Functional Constraints vs. Test Compression in Scan-Based Delay Testing
  2007 Jour. Electronic Testing, pages: 445 - 455
• Ilia Polian, Hideo Fujiwara
  Functional Constraints vs. Test Compression in Scan-Based Delay Testing
  2007 Conf. on Design, Automation and Test in Europe, volume: 23, issue: 5, pages: 445 - 455
  » show abstract« hide abstract
  Abstract

  We present an approach to prevent overtesting inscan-based delay test. The test data is transformed with respect tofunctional constraints while simultaneously keeping as manypositions as possible unspecified in order to facilitate testcompression. The method is independent of the employed delay faultmodel, ATPG algorithm and test compression technique, and it is easyto integrate into an existing flow. Experimental results emphasizethe severity of overtesting in scan-based delay test. Influence ofdifferent functional constraints on the amount of the required testdata and the compression efficiency is investigated. To the best ofour knowledge, this is the first systematic study on therelationship between overtesting prevention and test compression.
• Ilia Polian, Damian Nowroth, Bernd Becker
  Identification of Critical Errors in Imaging Applications
  2007 Int'l On-Line Test Symp., pages: 201 - 202
• Piet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker
  SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges
  2007 IEEE Asian Test Symp., pages: 433 - 438
  » show abstract« hide abstract
  Abstract

  A high-performance resistive bridging fault simulator SUPERB (Simulator Utilizing Parallel Evaluation of Resistive Bridges) is proposed. It is based on fault sectioning in combination with parallel-pattern or parallel-fault multiple-stuck-at simulation. It outperforms a conventional interval-based resistive bridging fault simulator by 60X to 120X while delivering identical results. Further competing tools are outperformed by several orders of magnitude.
• Stefan Spinner, Jie Jiang, Ilia Polian, Piet Engelke, Bernd Becker
  Simulating Open-Via Defects
  2007 IEEE Asian Test Symp., pages: 265 - 270
  » show abstract« hide abstract
  Abstract

  Open-via defects are a major systematic failure mechanism in nanoscale manufacturing processes. We present a flow for simulating open-via defects. Electrical parameters are extracted from the layout and technology data and represented in a way which allows efficient simulation on gate level. The simulator takes oscillation caused by open-via defects into account and quantifies its impact on defect coverage. The flow can be employed for manufacturing test as well as for defect diagnosis.
• Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich
  Test und Zuverlässigkeit Nanoelektronischer Systeme
  2007 GMM/GI/ITG Reliability and Design Conf., pages: 139 - 140

2006

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• Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
  Power Droop Testing
  2006 Int'l Conf. on Computer Design, pages: 243 - 250
• Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
  Simulating Resistive Bridging and Stuck-At Faults
  2006 IEEE Trans. on CAD, volume: 25, issue: 10, pages: 2181 - 2192
  » show abstract« hide abstract
  Abstract

  We present a simulator for resistive bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look-up, thus exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; interaction of fault effects in current time frame and earlier timeframes is elaborated on for different bridge resistances. Experimental results are given for resistive bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed and quantitative results with respect to all these definitions are given for the first time.
• Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker
  Analyzing the memory effect of resistive open in CMOS random logic
  2006 Int'l Conf. on Design and Test of Integrated Systems in Nanoscale Technology, pages: 251 - 256
  » show abstract« hide abstract
  Abstract

  This paper analyzes the electrical behaviour of resistive opens as a function of its unpredictable resistance. It is demonstrated that the electrical behaviour depends on the value of the open resistance. It is also shown that, due to the memory effect detection of the open by a given vector Ti depends on all the vectors that have been applied to the circuit before Ti. An electrical analysis of this memory effect is presented.
• Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
  Automatic Test Pattern Generation for Resistive Bridging Faults
  2006 Jour. Electronic Testing, volume: 22, issue: 1, pages: 61 - 69
  » show abstract« hide abstract
  Abstract

  An ATPG for resistive bridging faults in combinational or full-scan circuits is proposed. It combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced so far, it can handle static effects of arbitrary non-feedback bridges between two nodes, including ones detectable at higher bridge resistance and undetectable at lower resistance, and faults requiring more than one vector for detection. The developed tool is applied to ISCAS circuits, and a higher efficiency compared with other resistive bridging fault as well as stuck-at ATPG is reported. Information required for accurate resistive bridging fault simulation is obtained as a by-product.
• Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke
  X-Masking During Logic BIST and Its Impact on Defect Coverage
  2006 IEEE Trans. on VLSI Systems, volume: 14, issue: 2, pages: 193 - 202
  » show abstract« hide abstract
  Abstract

  We present a technique for making a circuit ready for Logic BIST by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.
• Jan Reineke, Björn Wachter, Stephan Thesing, Reinhard Wilhelm, Jochen Eisinger, Ilia Polian, Bernd Becker
  A Definition and Classification of Timing Anomalies
  2006 Int'l Workshop on Worst-Case Execution Time
• John P. Hayes, Ilia Polian, Bernd Becker
  A Model for Transient Faults in Logic Circuits
  2006 Int'l Design and Test Workshop
• Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker
  A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency
  2006 IEEE Asian Test Symp., pages: 273 - 278
  » show abstract« hide abstract
  Abstract

  This paper analyzes the electrical behavior of resistive opens as a function of their unpredictable resistance. It is demonstrated that the electrical behavior depends on the value of the open resistance. It is also shown that detection of the open by a given vector Ti recursively depends on all the vectors that have been applied to the circuit before Ti. An electrical analysis of this recursive effect is presented and a specific ATPG strategy is proposed.
• Stefan Spinner, M. Doelle, P. Ruther, Ilia Polian, Oliver Paul, Bernd Becker
  A System for Electro-Mechanical Reliability Testing of MEMS Devices
  2006 Int'l Symp. for Testing and Failure Analysis, pages: 147 - 152
• Sandip Kundu, Ilia Polian
  An Improved Technique for Reducing False Alarms Due to Soft Errors
  2006 Int'l On-Line Test Symp., pages: 105 - 110
  » show abstract« hide abstract
  Abstract

  A significant fraction of soft errors in modern microprocessors has been reported to never lead to a system failure. Any concurrent error detection scheme that raises alarm every time a soft error is detected will not be well heeded because most of these alarms are false and responding to them will affect system performance negatively. This paper improves state of the art in detecting and preventing false alarms. Existing techniques are enhanced by a methodology to handle soft errors on address bits. Furthermore, we demonstrate benefit of false alarm identification in implementing a roll-back recovery system by first calculating the optimum check pointing interval for a roll-back recovery system and then showing that the optimal number of check-points decrease by orders of magnitude when exclusion techniques are used even if the implementation of exclusion technique is not perfect.
• Jochen Eisinger, Ilia Polian, Bernd Becker, Alexander Metzner, Stephan Thesing, Reinhard Wilhelm
  Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis
  2006 IEEE Design and Diagnostics of Electronic Circuits and Systems, IEEE Computer Society, pages: 15 - 20
• Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich
  DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems)
  2006 it - Information Technology, volume: 48, issue: 5, page: 304
• Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker
  Delta-IddQ Testing of Resistive Short Defects
  2006 IEEE Asian Test Symp., pages: 63 - 68
  » show abstract« hide abstract
  Abstract

  This paper addresses the efficiency of IDDQ and more in particular Delta-IDDQ testing when using a realistic short defect model that properly considers the relation between the resistance of the short and its detectability. The results clearly show that the Delta-IDDQ approach covers a large number of resistive shorts missed by conventional logic testing, requiring only a relative small vector set. In addition a significant number of defects which are proven to be undetectable by logic testing but may deteriorate and result in reliability failures are detected. The Delta-IDDQ threshold and thus the equipment sensitivity is shown to be critical for the test quality. Furthermore, the validity of the traditional IDDQ fault models when considering resistive short defects is found to be limited. For instance, the use of the fault-free next-state function for sequential IDDQ fault simulation is shown to result in a wrong classification of some resistive short defects. This is the first systematic study of IDDQ testing of resistive short defects. The impact of the threshold on the defect coverage is quantified for the first time. Although the simulation results are based upon an older technology, the results and methodology are as well valid for state-of-the-art and NanoTechnologies.
• Stefan Spinner, J. Bartholomeyczik, Bernd Becker, M. Doelle, Oliver Paul, Ilia Polian, P. Roth, K. Seitz, P. Ruther
  Electromechanical Reliability Testing of Three-Axial Force Sensors
  2006 Design, Test, Integration and Packaging of MEMS/MOEMS, pages: 77 - 82
• Piet Engelke, Ilia Polian, Hans Manhaeve, Bernd Becker
  IddQ Testing of Resistive Bridging Defects
  2006 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, pages: 123 - 124
• Ilia Polian, Bernd Becker, M. Nakasato, S. Ohtake, Hideo Fujiwara
  Low-Cost Hardening of Image Processing Applications Against Soft Errors
  2006 Int'l Symp. on Defect and Fault Tolerance, pages: 274 - 279
  » show abstract« hide abstract
  Abstract

  s functionality. We call a soft error uncritical if its impact is provably limited to image perturbations during a very short period of time (number of cycles) and the system is guaranteed to recover thereafter. Uncritical errors do not require hardening as their effects are imperceivable for the human user of the system. We focus on soft errors in the motion estimation subsystem of MPEG-2 and introduce different definitions of uncritical soft errors in that subsystem. We propose a method to automatically determine uncritical errors and provide experimental results for various parameters. The concept can be adapted to further systems and enhance existing methods.
• Ilia Polian, Bernd Becker, M. Nakasato, S. Ohtake, Hideo Fujiwara
  Period of Grace: A New Paradigm for Efficient Soft Error Hardening
  2006 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
• Stefan Spinner, J. Bartholomeyczik, Bernd Becker, M. Doelle, Oliver Paul, Ilia Polian, R. Roth, K. Seitz, P. Ruther
  Reliability Testing of Three-Dimensional Silicon Force Sensors
  2006 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”

2005

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• Ilia Polian, Alejandro Czutro, Bernd Becker
  Evolutionary Optimization in Code-Based Test Compression
  2005 Conf. on Design, Automation and Test in Europe, pages: 1124 - 1129
• Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
  Modeling feedback bridging faults with non-zero resistance.
  2005 Jour. Electronic Testing, volume: 21, issue: 1, pages: 57 - 69
  » show abstract« hide abstract
  Abstract

  We study the behavior of feedback bridging faults with non-zero bridge resistance in both combinational and sequential circuits. We demonstrate that a test vector may detect the fault, not detect the fault or lead to oscillation, depending on bridge resistance. Moreover, the resistance intervals in which a particular behavior is observed are not necessarily contiguous. Even loops going through a gate with controlling values on its side inputs (which we call disabled loops) expose non-trivial behavior. We outline the multiple strengths problem which arises due to the fact that a critical bridge resistance depends on the strengths of the signals driving the bridge, which in turn are functions of the number of the on-transistors, these again depending on the bridge resistance, making such a fault very hard to resolve. For sequential circuits, we describe additional difficulties caused by the need to account for implications on bridge behavior, which have originated in the previous time frames. We conclude that the complexity of resistive feedback bridging fault simulation accurate enough to resolve such situations will probably be prohibitively high and propose possible simplifying assumptions. We present simulation results for ISCAS benchmarks using these assumptions with and without taking oscillation into account.
• John P. Hayes, Ilia Polian, Thomas Fiehn, Bernd Becker
  A Family of Logical Fault Models for Reversible Circuits
  2005 IEEE European Test Symp., pages: 65 - 70
  » show abstract« hide abstract
  Abstract

  Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional circuits such as stuck-at models are not well-suited to quantum circuits. We derive a family of logical fault models for reversible circuits composed of k-CNOT (k-input controlled-NOT) gates and implementable by many technologies. The models are extensions of the previously proposed single missing-gate fault (MGF) model, and include multiple and partial MGFs. We study the basic detection requirements of the new fault types and derive bounds on the size of their test sets. We also present optimal test sets computed via integer linear programming for various benchmark circuits. These results indicate that, although the test sets are generally very small, partial MGFs may need significantly larger test sets than single MGFs.
• Ilia Polian, John P. Hayes, Thomas Fiehn, Bernd Becker
  A Family of Logical Fault Models for Reversible Circuits
  2005 IEEE Asian Test Symp., pages: 422 - 427
  » show abstract« hide abstract
  Abstract

  Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional circuits such as stuck-at models are not well-suited to quantum circuits. We derive a family of logical fault models for reversible circuits composed of k-CNOT (k-input controlled-NOT) gates and implementable by many technologies. The models are extensions of the previously proposed single missing-gate fault (MGF) model, and include multiple and partial MGFs. We study the basic detection requirements of the new fault types and derive bounds on the size of their test sets. We also present optimal test sets computed via integer linear programming for various benchmark circuits. These results indicate that, although the test sets are generally very small, partial MGFs may need significantly larger test sets than single MGFs.
• Sandip Kundu, Matthew Lewis, Ilia Polian, Bernd Becker
  A Soft Error Emulation System for Logic Circuits
  2005 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, pages: 10 - 14
  » show abstract« hide abstract
  Abstract

  In nanometer technologies, soft errors in logic circuits are increasingly important. Since the failure in time (FIT) rates for these circuits are very low, millions of test vectors are required for a realistic analysis of soft errors. This exceeds the capabilities of software simulation tools. We propose an FPGA emulation architecture that can apply millions of vectors within seconds. Comprehensive soft error profiling was done for ISCAS 89 circuits. Soft errors were assigned to four different classes, and their latency and recovery time were obtained. This information is useful for understanding the vulnerability of the system to soft errors and hardening it against such errors.
• Sandip Kundu, Matthew Lewis, Ilia Polian, Bernd Becker
  A Soft Error Emulation System for Logic Circuits
  2005 Conf. on Design of Circuits and Integrated Systems, page: 137
  » show abstract« hide abstract
  Abstract

  In nanometer technologies, soft errors in logic circuits are increasingly important. Since the failure in time (FIT) rates for these circuits are very low, millions of test vectors are required for a realistic analysis of soft errors. This exceeds the capabilities of software simulation tools. We propose an FPGA emulation architecture that can apply millions of vectors within seconds. Comprehensive soft error profiling was done for ISCAS 89 circuits. Soft errors were assigned to four different classes, and their latency and recovery time were obtained. This information is useful for understanding the vulnerability of the system to soft errors and hardening it against such errors.
• M. Doelle, Stefan Spinner, P. Ruther, Ilia Polian, Oliver Paul, Bernd Becker
  A System for Determining the Impact of Mechanical Stress on the Reliability of MEMS
  2005 IEEE European Test Symp., pages: 57 - 61
  » show abstract« hide abstract
  Abstract

  This paper reports on an experimental test system which enables the automated analysis of mechanical stress impact on the reliability of microelectromechanical systems (MEMS). With this system, in-situ electrical characterization and optical inspection are performed while subjecting MEMS devices to defined mechanical loads. Impact objects of various geometries, e.g., contact probes or wafer prober needles, can be applied which are aligned relative to the MEMS device using an xyz-nanopositioning stage with an accuracy of 25 nm. This positioning stage enables programmable static forces up to 5 N and dynamic loads at frequencies up to 800 Hz. With this highly flexible system reliability tests, postmanufacturing tests and stress screens can be performed on single chips as well as on whole wafers with diameters up to 6 inch. Preliminary results on long-term reliability tests using CMOS-based stress sensors exploiting the piezoresistive effect in field effect transistors are presented.
• M. Doelle, Stefan Spinner, P. Ruther, Ilia Polian, Oliver Paul, Bernd Becker
  A System for Determining the Impact of Mechanical Stress on the Reliability of MEMS
  2005 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, pages: 88 - 89
  » show abstract« hide abstract
  Abstract

  This paper reports on an experimental test system which enables the automated analysis of mechanical stress impact on the reliability of microelectromechanical systems (MEMS). With this system, in-situ electrical characterization and optical inspection are performed while subjecting MEMS devices to defined mechanical loads. Impact objects of various geometries, e.g., contact probes or wafer prober needles, can be applied which are aligned relative to the MEMS device using an xyz-nanopositioning stage with an accuracy of 25 nm. This positioning stage enables programmable static forces up to 5 N and dynamic loads at frequencies up to 800 Hz. With this highly flexible system reliability tests, postmanufacturing tests and stress screens can be performed on single chips as well as on whole wafers with diameters up to 6 inch. Preliminary results on long-term reliability tests using CMOS-based stress sensors exploiting the piezoresistive effect in field effect transistors are presented.
• Ilia Polian, Hideo Fujiwara
  Functional Constraints vs. Test Compression in Scan-Based Delay Testing
  2005 IEEE Int'l GHz/Gbps Test Workshop, pages: 91 - 100
• Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
  Modeling feedback bridging faults with non-zero resistance
  2005 Jour. Electronic Testing, volume: 21, issue: 1, pages: 57 - 69
  » show abstract« hide abstract
  Abstract

  We study the behavior of feedback bridging faults with non-zero bridge resistance in both combinational and sequential circuits. We demonstrate that a test vector may detect the fault, not detect the fault or lead to oscillation, depending on bridge resistance. Moreover, the resistance intervals in which a particular behavior is observed are not necessarily contiguous. Even loops going through a gate with controlling values on its side inputs (which we call disabled loops) expose non-trivial behavior. We outline the multiple strengths problem which arises due to the fact that a critical bridge resistance depends on the strengths of the signals driving the bridge, which in turn are functions of the number of the on-transistors, these again depending on the bridge resistance, making such a fault very hard to resolve. For sequential circuits, we describe additional difficulties caused by the need to account for implications on bridge behavior, which have originated in the previous time frames. We conclude that the complexity of resistive feedback bridging fault simulation accurate enough to resolve such situations will probably be prohibitively high and propose possible simplifying assumptions. We present simulation results for ISCAS benchmarks using these assumptions with and without taking oscillation into account.
• Ilia Polian
  Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen
  2005 it - Information Technology, volume: 47, issue: 3, pages: 172 - 174
  » show abstract« hide abstract
  Abstract

  renden Entwurfsautomatisierungssoftware-Herstellers wird derzeit durchgeführt. Der zweite Teil der Dissertation befasst sich mit Entwurfsmethoden, welche die Testbarkeit des Schaltkreises auf dynamische Defekte erhöhen. Ein Ansatz zur Festlegung mehrerer Prüfpfade und eine Selbsttestarchitektur werden vorgestellt. Zwei Anhänge beschreiben den Zusammenhang zwischen den Nichtstandardfehlermodellen und dem konventionellen stuck-at-Modell und ihren Einsatz in der formalen Verifikation.
• Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker
  On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
  2005 IEEE Asian Test Symp., pages: 266 - 269
  » show abstract« hide abstract
  Abstract

  Resistive defects are gaining importance in very-deep-submicron technologies, but their detection conditions are not trivial. Test application can be performed under reduced temperature and/or voltage in order to improve detection of these defects. This is the first analytical study of resistive bridge defect coverage of CMOS ICs under low-temperature and mixed low-temperature, low-voltage conditions. We extend a resistive bridging fault model in order to account for temperature-induced changes in detection conditions. We account for changes in both the parameters of transistors involved in the bridge and the resistance of the short defect itself. Using a resistive bridging fault simulator, we determine fault coverage for low-temperature testing and compare it to the numbers obtained at nominal conditions. We also quantify the coverage of flaws,i.e. defects that are redundant at nominal conditions but could deteriorate and become early-life failures. Finally, we compare our results to the case of low-voltage testing and comment on combination of these two techniques.
• Ilia Polian, Sandip Kundu, Jean-Marc Galliere, Piet Engelke, Michel Renovell, Bernd Becker
  Resistive Bridge Fault Model Evolution From Conventional to Ultra Deep Submicron Technologies
  2005 VLSI Test Symp., pages: 343 - 348
  » show abstract« hide abstract
  Abstract

  We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) and a technology-specific part. The first model is based on Shockley equations and is valid for conventional but not deep submicron CMOS. The second model is obtained by fitting SPICE data. The third resistive bridging fault model uses Berkeley Predictive Technology Model and BSIM4; it is valid for CMOS technologies with feature sizes of 90nm and below, accurately describing non-trivial electrical behavior in that technologies. Experimental results for ISCAS circuits show that the test patterns obtained for the Shockley model are still valid for the Fitted model, but lead to coverage loss under the Predictive model.
• Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
  Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
  2005 IEEE Design and Diagnostics of Electronic Circuits and Systems, pages: 43 - 48
• Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
  Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
  2005 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, pages: 16 - 20
• Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
  Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
  2005 IEEE Int'l Workshop on Current and Defect-Based Testing, pages: 43 - 48
• Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker
  Transient Fault Characterization in Dynamic Noisy Environments
  2005 Int'l Test Conf., pages: 10 pp. - 1048

2004

 back to the year overview

• Ilia Polian, Bernd Becker, Alejandro Czutro
  Compression Methods for Path Delay Fault Test Pair Sets: A Comparative Study
  2004 IEEE European Test Symp., pages: 263 - 264
• Ilia Polian, Irith Pomeranz, Sudhakar M. Reddy, Bernd Becker
  On the use of maximally dominating faults in n-detection test generation
  2004 IEE Proceedings Computers and Digital Techniques, volume: 151, issue: 3, pages: 235 - 244
  » show abstract« hide abstract
  Abstract

  The size of an n-detection test set increases approximately linearly with n. This increase in size may be too fast when an upper bound on test set size must be satisfied. We propose a test generation method for obtaining a more gradual increase in the sizes of n-detection test sets, while still ensuring that every additional test would be useful in improving the test set quality. The method is based on the use of fault dominance relations to identify a small subset of faults (called maximally dominating faults) whose numbers of detections are likely to have a high impact on the defect coverage of the test set. We use structural analysis to obtain a superset of the maximally dominating fault set. We also propose a method for determining exact sets of maximally dominating faults. We define new types of n-detection test sets based on the approximate and exact sets of maximally dominating faults. The test sets are called (n,n2)-detection test sets and (n,n2,n3)-detection test sets. We present experimental results to demonstrate the usefulness of these test sets in producing high-quality n-detection test sets for the combinational logic of ISCAS-89 benchmark circuits.
• Ilia Polian, Bernd Becker
  Scalable Delay Fault BIST For Use With Low-Cost ATE
  2004 Jour. Electronic Testing, volume: 20, issue: 2, pages: 181 - 197
  » show abstract« hide abstract
  Abstract

  We present a BIST architecture based on Multi-Input Signature Register (MISR) expanding single input vectors into sequences, which are used for testing of delay faults. Input vectors can be stored on-chip or in the ATE; in the latter case, a low speed tester can be employed though the sequences are applied at-speed to block-under-test. The number of input vectors (and thus the area demand on-chip or ATE memory requirements) can be traded for the test application time. The block-under-test can be switched off for some amount of time between application of consecutive input vectors. We provide arguments why this approach may be the only way to meet thermal and power constraints. Furthermore, we demonstrate how the BIST scheme can use these cool-down breaks for re-configuration. We propose two methods for generating input vectors, a straight-forward one and one using BDDs and symbolic state traversals. As both require only a two-pattern test as input, IP cores can be handled by these methods.
• Yuyi Tang, Hans-Joachim Wunderlich, Harald Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
  X-masking during logic BIST and its impact on defect coverage
  2004 IEEE Int'l Workshop on Test Resource Partitioning, pages: 442 - 451
• Ilia Polian
  On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications
  VDI-Verlag, 2004
• Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
  Automatic test pattern generation for resistive bridging faults
  2004 IEEE European Test Symp., pages: 160 - 165
• Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
  Automatic test pattern generation for resistive bridging faults
  2004 IEEE Int'l Workshop on Current and Defect-Based Testing, pages: 89 - 94
• Bernd Becker, Markus Behle, Friedrich Eisenbrand, Martin Fränzle, Marc Herbstritt, Christian Herde, Jörg Hoffmann, Daniel Kröning, Bernhard Nebel, Ilia Polian, Ralf Wimmer
  Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems
  2004 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Shaker Verlag, pages: 65 - 75
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  Abstract

  We present a concept to significantly advance the state of the art for bounded model checking (BMC) and inductive verification (IV) of hybrid discrete-continuous systems. Our approach combines the expertise of partners coming from different domains, like hybrid systems modeling and digital circuit verification, bounded planning and heuristic search, combinatorial optimization and integer programming. After sketching the overall verification flow we present first results indicating that the combination and tight integration of different verification engines is a first step to pave the way to fully automated BMC and IV of medium to large-scale networks of hybrid automata.
• Ilia Polian
  On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications.
  GI, volume: D-4, pages: 169 - 178, 2004
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  Abstract

  Konventionelle Testverfahren für integrierte Schaltungen sind zunehmend nicht mehr in der Lage, akzeptable Produktqualität zu gewährleisten. Ein möglicher Ausweg ist der Einsatz von verbesserten Modellen für Fertigungsdefekte (Nichtstandardfehlermodelle). Der erste Teil der Dissertation beschäftigt sich deshalb mit der Modellierung von so genannten Brückenfehlern, welche insbesondere partikelinduzierte Kurzschlüsse modellieren und daher näher an realistischen Defekten sind als die gewöhnlich betrachteten stuck-at-Fehler. Insbesondere die Berücksichtigung des Einflusses des Kurzschlusswiderstandes spiegelt die Gegebenheiten moderner Deep-Submicron-Technologien wider. Obwohl ein Kontinuum von Defekten unter Berücksichtigung nichttrivialer elektrischer Zusammenhänge modelliert wird, sind effiziente diskrete Simulationsalgorithmen möglich. Die einfachsten der vorgestellten Modelle wurden für den industriellen Einsatz optimiert; die Integration der komplexeren resistiven Modelle in die Werkzeuge eines führenden Entwurfsautomatisierungssoftware-Herstellers wird derzeit durchgeführt. Eine weitere zunehmend wichtige Defektklasse stellen die Verzögerungsdefekte dar, welche so genanntes Zweimustertesten erfordern. Der zweite Teil der Dissertation befasst sich mit Entwurfsmethoden, welche die Testbarkeit des Schaltkreises auf dynamische Defekte erhöhen. Ein Ansatz zur Festlegung mehrerer Prüfpfade und eine Selbsttestarchitektur werden vorgestellt. Zwei Anhänge beschreiben den Zusammenhang zwischen den Nichtstandardfehlermodellen und dem konventionellen stuck-at-Modell und ihren Einsatz in der formalen Verifikation.
• John P. Hayes, Ilia Polian, Bernd Becker
  Testing for Missing-Gate Faults in Reversible Circuits
  2004 IEEE Asian Test Symp., pages: 100 - 105
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  Abstract

  Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of reversible elements called k-CNOT (controllable NOT) gates. We review the characteristics of k-CNOT circuits and observe that traditional fault models like the stuck-at model may not accurately represent their faulty behavior or test requirements. A new fault model, the missing gate fault (MGF) model, is proposed to better represent the physical failure modes of quantum technologies. It is shown that MGFs are highly testable, and that all MGFs in an N-gate k-CNOT circuit can be detected with from one to | N / 2 | test vectors. A design-for-test (DFT) method to make an arbitrary circuit fully testable for MGFs using a single test vector is described. Finally, we present simulation results to determine (near) optimal test sets and DFT configurations for some benchmark circuits.
• Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
  The Pros and Cons of Very-Low-Voltage Testing: An Analysis Based on Resistive Short Defects
  2004 VLSI Test Symp., pages: 171 - 178
• Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
  The Pros and Cons of Very-Low-Voltage Testing: An Analytical View
  2004 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, pages: 149 - 153
• Yuyi Tang, Hans-Joachim Wunderlich, Harald Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
  X-masking during logic BIST and its impact on defect coverage
  2004 Int'l Test Conf., pages: 442 - 451
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  Abstract

  We present a technique for making a circuit ready for Logic BIST by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.

2003

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• Ilia Polian, Bernd Becker
  Configuring MISR-Based Two-Pattern BIST Using Boolean Satisfiability
  2003 IEEE Design and Diagnostics of Electronic Circuits and Systems, pages: 73 - 80
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  Abstract

  Most known two-pattern BIST architectures require prohibitive test application times in order to obtain high delay fault coverage. In an earlier work, a BIST TPG block based on a MISR expanding input vectors into test sequences of length 2^n has been refined such that shorter sequences could be used. By doing so, spectacular reductions of test application time were achieved. However, the procedures for computing input vectors were based on BDD-backed state traversal or extensive simulation, and their run-time requirements were tremendous. In this work, we propose a SAT-based input vector generation method, which leads to test application times that are similar to the earlier method, but with significantly reduced computational effort. For the first time, we present experimental results for larger ISCAS benchmarks, which previous methods could not treat. Furthermore, we discuss the application of our method when the requirement to apply the complete test pair set is relaxed.
• Ilia Polian, Bernd Becker, Sudhakar M. Reddy
  Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST
  2003 Conf. on Design, Automation and Test in Europe, pages: 1184 - 1185
• Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
  Modelling Feedback Bridging Faults With Non-Zero Resistance
  2003 European Test Workshop, pages: 91 - 96
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  Abstract

  We study the behavior of feedback bridging faults with non-zero bridge resistance in both combinational and sequential circuits. We demonstrate that a test vector may detect the fault, not detect the fault or lead to oscillation, depending on bridge resistance. Moreover, the resistance intervals in which a particular behavior is observed are not necessarily contiguous. Even loops going through a gate with controlling values on its side inputs (which we call disabled loops) expose non-trivial behavior. We outline the multiple strengths problem which arises due to the fact that a critical bridge resistance depends on the strengths of the signals driving the bridge, which in turn are functions of the number of the on-transistors, these again depending on the bridge resistance, making such a fault very hard to resolve. For sequential circuits, we describe additional difficulties caused by the need to account for implications on bridge behavior, which have originated in the previous time frames. We conclude that the complexity of resistive feedback bridging fault simulation accurate enough to resolve such situations will probably be prohibitively high and propose possible simplifying assumptions. We present simulation results for ISCAS benchmarks using these assumptions with and without taking oscillation into account.
• Ilia Polian, Bernd Becker
  Multiple Scan Chain Design for Two-Pattern Testing
  2003 Jour. Electronic Testing, volume: 19, issue: 1, pages: 37 - 48
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  Abstract

  Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.
• Ilia Polian, Wolfgang Günther, Bernd Becker
  Pattern-Based Verification of Connections to Intellectual Property Cores
  2003 INTEGRATION, the VLSI Jour., volume: 35, issue: 1, pages: 25 - 44
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  Abstract

  Verification of designs containing pre-designed cores is a challenging topic in modern IC design, since traditional approaches generally do not use the information that parts of the design (like IP cores) are already verified. The Port Order Fault Model (POF) has recently been introduced for detecting design errors occurring during integration of a core into a System-on-Chip or during test logic insertion. In this work, we generate verification patterns with 100 percent coverage of a sub-class of POF, called 2-POF. We provide theoretical arguments and experimental results backing the efficiency of these patterns also for detecting higher-order POFs. Moreover, verification pattern sets generated by our approach are more compact compared to the results published before.
• Ilia Polian, Bernd Becker
  Reducing ATE Cost in System-on-Chip
  2003 IFIP VLSI-SoC, pages: 337 - 342
• Ilia Polian, Bernd Becker
  Reducing ATE Cost in System-on-Chip Test
  2003 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, pages: 34 - 37
• Ilia Polian, Bernd Becker
  Reducing ATE Cost in System-on-Chip Test
  2003 IEEE Int'l Workshop on Test Resource Partitioning
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  Abstract

  Traditional SoC test scheduling approaches minimize test time under additional constraints. We argue that test costs are not determined by test time alone. Indeed, the speed of used ATE channels influences both cost and test time. We present a case for using a mixture of high-speed and low-cost ATE channels. Two heuristics and an exact algorithm are used. Experimental results show that such a mixture scenario can reduce the cost with no impact on test time.
• J. Bradford, H. Delong, Ilia Polian, Bernd Becker
  Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
  2003 Jour. Electronic Testing, volume: 19, issue: 4, pages: 387 - 395
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  Abstract

  Three different techniques for simulating realistic faults generated from IC layout are discussed. Two of them deal with bridging faults, and the third one handles crosstalk faults. The simulation is performed on top of a commercial simulator and thus is very well applicable in an industrial environment. No change of the design database and only minimal changes of the test shell are required. Experimental results are reported for a library cell and a block from a full-custom design.
• Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
  Simulating Resistive Bridging Faults
  2003 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, pages: 92 - 97
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  Abstract

  We present a simulator for resistive bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look-up, thus exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; reciprocal action of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed and quantitative results with respect to all these definitions are given for the first time.
• Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
  Simulating Resistive Bridging and Stuck-At Faults
  2003 Int'l Test Conf., pages: 1051 - 1059
• Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
  Simulating Resistive Bridging and Stuck-at Faults
  2003 IEEE Int'l Workshop on Current and Defect-Based Testing, pages: 49 - 56
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  Abstract

  We present a simulator for resistive bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look-up, thus exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; reciprocal action of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed and quantitative results with respect to all these definitions are given for the first time.
• Ilia Polian, Wolfgang Günther, Bernd Becker
  The Case For 2-POF
  2003 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pages: 164 - 173
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  Abstract

  The Port Order Fault Model (POF) has recently been introduced for detecting design errors occuring during integration of a core into a System-on-Chip or during test logic insertion. In an earlier work, we generated verification vectors with 100 percent coverage of a sub-class of POF, called 2-POF. Demonstrating empirically that these sets of verification vectors also cover an other sub-class of POF, 3-POF, almost completely, we concluded their efficiency also for higher-order POFs. In this paper, we provide theoretical arguments and more empirical results supporting the claim that verification vectors with high coverage of lower-order POFs are very likely to be also efficient in detecting higher-order POFs.
• Ilia Polian, Wolfgang Günther, Bernd Becker
  The Case For 2-POF
  2003 IEEE Design and Diagnostics of Electronic Circuits and Systems, pages: 291 - 292

2002

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• Ilia Polian, Piet Engelke, Bernd Becker
  Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics
  2002 Int'l Symp. on Multi-Valued Logic, pages: 216 - 222
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  Abstract

  We present the concept of a multi-valued logic simulator for bridging faults in sequential circuits. Different models for the handling of intermediate values in flip-flops on the digital design level can be integrated and result in an Expected realistic behavior area for bridging faults. Several experimental results are given to underline properties and advantages of the simulation technique
• Ilia Polian, Irith Pomeranz, Bernd Becker
  Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests
  2002 IEEE Asian Test Symp., pages: 9 - 14
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  Abstract

  n-detection test sets for stuck-at faults have been shown to be useful in detecting unmodeled defects. It was also shown that a set of faults, called maximally dominating faults, can play an important role in controlling the increase in the size of an n-detection test set as n is increased. In an earlier work, a superset of the maximally dominating fault set was used. In this work, we propose a method to determine exact sets of maximally dominating faults. We also define a new type of n-detection test sets based on the exact set of maximally dominating faults. We present experimental results to demonstrate the usefulness of this exact set in producing high-quality n-detection test sets.
• Ilia Polian, Irith Pomeranz, Bernd Becker
  Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests
  2002 European Test Workshop
• Ilia Polian, Bernd Becker
  Go BIST
  2002 IEEE Int'l Online Testing Workshop, pages: 147 - 151
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  Abstract

  A BIST method enabling two-pattern testing at-speed without violating thermal constraints by introducing cool down periods is proposed. The application of the method is demonstrated based on a scalable BIST architecture. Applicability on IP cores is given since only a two-pattern test set is required as input.
• Ilia Polian, Bernd Becker
  Optimal Bandwidth Allocation in Concurrent SoC Test Under Pin Number Constraints
  2002 Workshop on RTL and High Level Testing, pages: 12 - 17
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  Abstract

  A method for assigning pins to cores in concurrent System-on-Chip testing is proposed. For each core, the number of assigned pins is traded for test application time using multiple scan chains. Given a pin number constraint, the overall test time is minimized. The used algorithm is formally proven to be optimal, although it has low polynomial computational complexity. The approach is applicable to any kind of testing which requires transport of test data from test equipment to the cores, including scan testing and scan-based BIST.
• J. Bradford, H. Delong, Ilia Polian, Bernd Becker
  Realistic Fault Simulation in an Industrial Setting
  2002 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
• Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker
  Sequential n-Detection Criteria: Keep It Simple!
  2002 IEEE Int'l Online Testing Workshop, pages: 189 - 190
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  Abstract

  The idea of n-detection is to exposure a target fault in n different ways. To denote several detections as `sufficiently different', formal criteria seem to be necessary. In this article, we study the properties of test sequences with respect to four new criteria, which we call difference types. We try to guide the n-detection test sequence generation process for stuck-at faults by difference types and evaluate coverage of a Surprisingly, we have found out that the effectiveness in detecting non-target faults is not affected beyond statistical noise. In our opinion this result underlines the effectiveness of n-detection without sophisticated differentiation criteria.
• J. Bradford, H. Delong, Ilia Polian, Bernd Becker
  Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
  2002 European Test Workshop, pages: 75 - 80

2001

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• Ilia Polian, Wolfgang Günther, Bernd Becker
  Efficient Pattern-Based Verification of Connections to Intellectual Property Cores
  2001 IEEE Asian Test Symp., pages: 443 - 448
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  Abstract

  Verification of designs containing pre-designed cores is a challenging topic in modern IC design, since traditional approaches generally do not use the information that parts of the design are already verified (like IP cores). To verify the connectivity between the surrounding design and IP cores, we propose a method that is based on test patterns. Using only those patterns for simulation, in almost all cases 100 percent of the errors can be detected. Existing test access logic is employed for the application of the patterns. A large set of experimental results is given to demonstrate the efficiency of the approach.
• Ilia Polian, Wolfgang Günther, Bernd Becker
  Efficient Pattern-Based Verification of Connections to Intellectual Property Cores
  2001 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pages: I:111 - 120
• Ilia Polian, Bernd Becker
  Multiple Scan Chain Design for Two-Pattern Testing
  2001 VLSI Test Symp., pages: 88 - 93
• Ilia Polian, Bernd Becker
  Multiple Scan Chain Design for Two-Pattern Testing
  2001 Latin-American Test Workshop, pages: 156 - 161
• Ilia Polian, Bernd Becker
  Multiple Scan Chain Design for Two-Pattern Testing
  2001 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”

1999

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• Martin Keim, Ilia Polian, Harry Hengster, Bernd Becker
  A Scalable BIST Architecture for Delay Faults
  1999 European Test Workshop, pages: 98 - 103
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  Abstract

  In this paper we present a scalable BIST (Built-In Self Test) architecture that provides a tunable trade-off between on-chip area demand and test execution time for delay fault testing. So, the architecture can meet test execution time requirements or available area requirements or any target in between. Experiments show the scalability of our approach, e.g. that considerably shorter test execution time can be achieved by storing only a few additional input vectors of the BIST architecture. The gain of test execution time possible with the proposed method ranges from a factor of 2 up to a factor of more than 800000.