2008

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• Thomas Eschbach, Bernd Becker
  Interactive Circuit Diagram Visualization
  2008 Computer Graphics and Imaging, ACTA Press, pages: 218 - 223

2006

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• Thomas Eschbach, Wolfgang Günther, Bernd Becker
  Orthogonal Hypergraph Drawing for Improved Visibility
  2006 Journal of Graph Algorithms and Applications, volume: 10, issue: 2, pages: 141 - 157
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  Abstract

  Visualization of circuits is an important research area in electronic design automation. One commonly accepted method to visualize a circuit aligns the gates to layers and uses orthogonal lines to connect the gates. In our model we assume that between two consecutive layers every net is allowed to occupy only one track. This avoids unnecessary bends in the wires and helps to improve the clarity of the drawing. Then a crossing reduction step is applied to further improve the readability of the circuit schematics.First we assume that the nodes have already been fixed on alayered hypergraph structure. We consider the problem of assigning the hyperedges between two layers to tracks. The idea is to minimize the total number of hyperedge crossings. We prove that finding the best solution is NP-hard. Then, in contrast to many other approaches which route all the wiring after placing all nodes we focus on a new approach which dynamically reorders the nodes within the layers to further reduce the number of hyperedge crossings.An efficient algorithm is presented that minimizes the hyperedge crossings. Experimental results are provided which show that the drawings can be improved significantly while the run time remains moderate.

2005

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• Martina Welte, Thomas Eschbach, Bernd Becker
  Automated Text Extraction And Indexing Of Video Presentation Recordings For Keyword Search Via A Web Interface
  2005 Workshop eLectures - Einsatzmöglichkeiten, Herausforderungen und Forschungsperspektiven, Logos Verlag Berlin
• Martina Welte, Thomas Eschbach, Bernd Becker
  Automated Text Extraction And Indexing Of Video Presentation Recordings For Keyword Search Via A Web Interface
  2005 AACE World Conf. on E-Learning in Corporate, Government, Healthcare, and Higher Education, AACE Press, pages: 3200 - 3205
• Thomas Eschbach, Wolfgang Günther, Bernd Becker
  Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases
  2005 Int'l Conf. on VLSI Design, pages: 433 - 438

2004

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• Thomas Eschbach, Wolfgang Günther, Bernd Becker
  Orthogonal Hypergraph Routing for Improved Visibility
  2004 Great Lakes Symp. on VLSI, pages: 385 - 388
• Thomas Eschbach, Rolf Drechsler, Bernd Becker
  Placement and Routing Optimization for Circuits Derived from BDDs
  2004 IEEE Int'l Symp. on Circuits and Systems, pages: V229 - V232

2003

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• Thomas Eschbach, Wolfgang Günther, Bernd Becker
  Crossing Reduction for Orthogonal Circuit Visualization
  2003 Int'l Conf. on VLSI, CSREA Press, pages: 107 - 113
• Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, L. Linhard, G. Angst
  Recursive Bi-Partitioning of Netlists for Large Number of Partitions
  2003 Journal of Systems Architecture, volume: 49, issue: 12-15, pages: 521 - 528

2002

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• Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker
  Crossing Reduction by Windows Optimization
  2002 Int'l Symp. on Graph Drawing, volume: 2528, pages: 285 - 294
• Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, L. Linhard, G. Angst
  Recursive Bi-Partitioning of Netlists for Large Number of Partitions
  2002 Euromicro Conf., pages: 38 - 44

2001

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• Bernd Becker, Rolf Drechsler, Thomas Eschbach, Wolfgang Günther
  GREEDY IIP: Partitioning Large Graphs by Greedy Iterative Improvement
  2001 Euromicro Conf., pages: 54 - 60