2016

 back to the year overview

• Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
  Effective Generation and Evaluation of Diagnostic SBST Programs
  2016 IEEE VLSI Test Symposium
• Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
  A Flexible Framework for the Automatic Generation of SBST Programs
  2016 IEEE Transactions on Very Large Scale Integration (VLSI) Systems, volume: 24, issue: 10, pages: 3055 - 3066

2015

 back to the year overview

• Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
  On the Automatic Generation of SBST Test Programs for In-Field Test
  2015 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
• Andreas Riefert, Matthias Sauer, Sudhakar Reddy, Bernd Becker
  Improving Diagnosis Resolution of a Fault Detection Test Set
  2015 VLSI Test Symposium
  » show abstract« hide abstract
  Abstract

  In this work we present a method to improve the diagnosis resolution of a compact fault detection test set without increasing pattern count or decreasing fault coverage. The basic idea of the approach is to generate a SAT formula which enforces diagnosis and is solved by a MAX-SAT solver which is a SAT-based maximization tool. We believe this is the first time a method to improve diagnosis resolution of a test set of given size has been reported. Experimental results on ISCAS 89 circuits demonstrate the effectiveness of the proposed method.
• Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
  On the Automatic Generation of SBST Test Programs for In-Field Test
  2015 Conf. on Design, Automation and Test in Europe

2014

 back to the year overview

• Andreas Riefert, Lyl Ciganda, Matthias Sauer, Paolo Bernadi, Matteo Sonza Reorda, Bernd Becker
  An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults
  2014 Conf. on Design, Automation and Test in Europe
  » show abstract« hide abstract
  Abstract

  Functional microprocessor test methods provide several advantages compared to DFT approaches, like reduced chip cost and at-speed execution. However, the automatic generation of functional test patterns is an open issue. In this work we present an approach for the automatic generation of functional microprocessor test sequences for small-delay faults based on Bounded Model Checking. We utilize an ATPG framework for small-delay faults in sequential, non-scan circuits and propose a method for constraining the input space for generating functional test sequences (i.e., test programs). We verify our approach by evaluating the miniMIPS microprocessor. In our experiments we were able to reach over 97 % fault efficiency. To the best of our knowledge, this is the first fully automated approach to functional microprocessor test for small-delay faults.

2013

 back to the year overview

• Andreas Riefert, Joerg Mueller, Matthias Sauer, Wolfram Burgard, Bernd Becker
  Identification of Critical Variables using an FPGA-based Fault Injection Framework
  2013 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
• Andreas Riefert, Joerg Mueller, Matthias Sauer, Wolfram Burgard, Bernd Becker
  Identification of Critical Variables using an FPGA-based Fault Injection Framework
  2013 VLSI Test Symp., pages: 1 - 6
  » show abstract« hide abstract
  Abstract

  The shrinking nanometer technologies of modern microprocessors and the aggressive supply voltage down-scaling drastically increase the risk of soft errors. In order to cope with this risk efficiently, selective hardware and software protection schemes are applied. In this paper, we propose an FPGA-based fault injection framework which is able to identify the most critical registers of an entire microprocessor. Further-more, our framework identifies critical variables in the source code of an arbitrary application running in its native environment. We verify the feasibility and relevance of our approach by implementing a lightweight and efficient error correction mechanism protecting only the most critical parts of the system. Experimental results with state estimation applications demonstrate a significantly reduced number of critical calculation errors caused by faults injected into the processor.