1999

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• Martin Keim, Ilia Polian, Harry Hengster, Bernd Becker
  A Scalable BIST Architecture for Delay Faults
  1999 European Test Workshop, pages: 98 - 103
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  Abstract

  In this paper we present a scalable BIST (Built-In Self Test) architecture that provides a tunable trade-off between on-chip area demand and test execution time for delay fault testing. So, the architecture can meet test execution time requirements or available area requirements or any target in between. Experiments show the scalability of our approach, e.g. that considerably shorter test execution time can be achieved by storing only a few additional input vectors of the BIST architecture. The gain of test execution time possible with the proposed method ranges from a factor of 2 up to a factor of more than 800000.
• Harry Hengster, Bernd Becker
  Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability -
  1999 Int'l Symp. on Defect and Fault Tolerance, pages: 268 - 275

1998

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• Harry Hengster, Bernd Becker
  Synthesis of Fully Testable High Speed Circuits Derived from Decision Diagrams
  1998 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
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  Abstract

  We present an approach to synthesize fully stuck-at fault testable circuits along with complete test sets. Starting from functional descriptions given by Kronecker Functional Decision Diagrams (KFDDs) circuits with inherently small delay are constructed by a composition method based on Boolean Matrix Multiplication. During the construction efficient algorithms working on the KFDD are used to avoid the creation of constant lines. Furthermore, in each composition step tests for the faults at the newly generated lines are computed on the fly. Experimental results are given to underline the efficiency of the methods.
• Harry Hengster, Bernd Becker
  Synthesis of Fully Testable High Speed Circuits Derived from Decision Diagrams
  1998 Int'l Workshop on Logic Synth., pages: 341 - 345
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  Abstract

  We present an EXOR-based synthesis approach to obtain fully stuck-at fault testable circuits along with complete test sets. Starting from functional descriptions given by Kronecker Functional Decision Diagrams (KFDDs) circuits with inherently small delay are constructed by a composition method based on Boolean Matrix Multiplication. During the construction efficient algorithms working on the KFDD are used to avoid the creation of constant lines. Furthermore, in each composition step tests for the faults at the newly generated lines are computed on the fly. Experimental results are given to underline the efficiency of the methods.

1997

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• Harry Hengster, Bernd Becker
  Synthesis of Fully Testable High Speed Circuits Derived from Decision Diagrams
  , 1997
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  Abstract

  We present an approach to synthesize fully stuck-at fault testable circuits along with complete test sets. Starting from functional descriptions given by Kronecker Functional Decision Diagrams (KFDDs) circuits with inherently small delay are constructed by a composition method based on Boolean Matrix Multiplication. During the construction efficient algorithms working on the KFDD are used to avoid the creation of constant lines. Furthermore, in each composition step tests for the faults at the newly generated lines are computed on the fly. Experimental results are given to underline the efficiency of the methods.
• Rolf Drechsler, Harry Hengster, H. Schäfer, J. Hartmann, Bernd Becker
  Testability of 2-Level AND/EXOR Expressions
  1997 European Design and Test Conf., pages: 548 - 553
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  Abstract

  It is often stated that AND/EXOR circuits are much easier testable than AND/OR circuits. This statement only holds for restricted classes of AND/EXOR expressions, like positive polarity Reed-Muller expressions and fixed polarity Reed-Muller expressions. For these two classes of circuits good deterministic testability properties are known. In this paper we show that for these circuits also good random pattern testability can be proven. An input probability distribution is given which yields a short expected test length for biased random patterns. This is the first time that theoretical results on random pattern testability are presented for 2-level AND/EXOR circuit realizations of arbitrary Boolean functions. For more general classes of 2-level AND/EXOR circuits analogous results are not proven. We present experimental results that show that in general minimized 2-level AND/OR circuits are as well (or badly) testable as minimized 2-level AND/EXOR circuits.

1996

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• Harry Hengster, Rolf Drechsler, S. Eckrich, T. Pfeiffer, Bernd Becker
  AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth
  1996 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
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  Abstract

  Decision diagrams are used in design automation for efficient representation of Boolean functions. But it is also possible to derive circuits directly from decision diagrams. In this paper we present an approach to synthesize circuits from a very general class of decision diagrams, the ordered Kronecker functional decision diagrams. We investigate area, depth and testability of the synthesized circuits and compare them to circuit designs generated by other synthesis tools. Experimental results show that the presented approach is suitable to overcome the trade-off between depth and testability.
• Harry Hengster, Rolf Drechsler, S. Eckrich, T. Pfeiffer, Bernd Becker
  AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth
  1996 IEEE Asian Test Symp., pages: 148 - 154
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  Abstract

  Decision Diagrams are used in design automation for efficient representation of Boolean functions. It is also possible to directly derive circuits from Decision Diagrams. In this paper we present an approach to synthesize circuits from a very general class of Decision Diagrams, the ordered Kronecker Functional Decision Diagrams. These Decision Diagrams make use of Davio decompositions which are based on exclusive-or operations and therefore allow the use of EXOR gates in the synthesized circuits. We investigate area, depth, and testability of these circuits and compare them to circuit designs generated by other synthesis tools. Experimental results show that the presented approach is suitable to overcome the trade-off between depth and testability at the price of reasonable area overhead.
• Harry Hengster, U. Sparmann, Bernd Becker, Sudhakar M. Reddy
  Local Transformations and Robust Dependent Path Delay Faults
  1996 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
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  Abstract

  Local transformations are used in several synthesis approaches. During application of such transformations attention has to be paid to many important properties, e.g. area, speed, power consumption, and testability. In this paper we study relations between local transformations and delay fault testability. In delay testing it is not necessary to test every path in a circuit to ascertain correct timing behavior. For example, a set of robust dependent path delay faults need not to be considered for testing if all paths that are not robust dependent are tested. We will present sufficient conditions for local transformations which ensure that a test set for all non-robust-dependent paths in the original circuit is also a test set for all non-robust-dependent paths in the transformed circuit. These conditions are applied to some local transformations which are often used in logic synthesis and it is shown that they preserve testability. The impact of local transformations on robust dependent testability is demonstrated by experimental results performed on benchmark circuits.
• Harry Hengster, U. Sparmann, Bernd Becker, Sudhakar M. Reddy
  Local Transformations and Robust Dependent Path Delay Faults
  1996 European Test Workshop
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  Abstract

  Local transformations are used in several synthesis approaches. During application of such transformations attention has to be paid to many important properties, e.g. area, speed, power consumption, and testability. In this paper we study relations between local transformations and delay fault testability. In delay testing it is not necessary to test every path in a circuit to ascertain correct timing behavior. For example, a set of robust dependent path delay faults need not to be considered for testing if all paths that are not robust dependent are tested. We present sufficient conditions for local transformations which ensure that a test set for all non-robust-dependent paths in the original circuit is also a test set for all non-robust-dependent paths in the transformed circuit. These conditions are applied to some local transformations which are often used in logic synthesis and it is shown that they preserve testability. The impact of local transformations on robust dependent testability is demonstrated by experimental results performed on benchmark circuits.
• Harry Hengster, U. Sparmann, Bernd Becker, Sudhakar M. Reddy
  Local Transformations and Robust Dependent Path Delay Faults
  1996 Int'l Test Conf.
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  Abstract

  Local transformations are used in several synthesis approaches. During application of such transformations attention has to be paid to many important properties, e.g. area, speed, power consumption, and testability. In this paper we study relations between local transformations and delay fault testability. In delay testing it is not necessary to test every path in a circuit to ascertain correct timing behavior. For example, a set of robust dependent path delay faults need not be considered for testing if all paths that are not robust dependent are tested. We present sufficient conditions for local transformations which ensure that a test set for all non-robust-dependent paths in the original circuit is also a test set for all non-robust-dependent paths in the transformed circuit. These conditions are applied to some local transformations which are often used in logic synthesis and it is shown that they preserve testability. The impact of local transformations on robust dependent testability is demonstrated by experimental results performed on benchmark circuits.
• Rolf Drechsler, Harry Hengster, H. Schäfer, Bernd Becker
  Testability of AND/EXOR Expressions
  1996 European Test Workshop
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  Abstract

  It is often stated that AND/EXOR circuits are much easier testable than AND/OR circuits. In this paper we show that this is not true for all 2-level circuits based on EXOR. The statement only holds for restricted classes of AND/EXOR expressions, like Positive Polarity Reed-Muller Expressions and Fixed Polarity Reed-Muller Expressions. AND/EXOR circuits are studied with respect to deterministic and random pattern testability. We present experimental results that show that in general minimized 2-level AND/OR circuits are as well (or badly) testable as minimized 2-level AND/EXOR circuits.

1995

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• Harry Hengster, Rolf Drechsler, Bernd Becker
  AND/OR/EXOR based Synthesis of KFDD-Circuits with Small Depth
  1995 Reed-Muller Colloquium UK
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  Abstract

  Construction of circuits from Decision Diagrams (DDs) has shown several advantages, e.g. the resulting circuits have nice testability properties. One major drawback of circuits derived from ordered DDs is that their depth is proportional to the number of inputs. In this paper we present an approach to design DD circuits derived from Kronecker Functional DDs (KFDDs) with small depth. Experimental results are given that show the efficiency of our approach.

1994

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• Harry Hengster, Rolf Drechsler, Bernd Becker
  Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model
  1994 Int'l Conf. on VLSI Design, pages: 123 - 126
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  Abstract

  We present a new approach to show that local circuit transformations which improve the area of a circuit preserve or improve robust path-delay-fault testability. In contrast to previously published methods which had to consider the whole circuit we examine only the subcircuits to be transformed. Furthermore, we present some transformations which preserve or improve testability.

1993

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• Bernd Becker, Rolf Drechsler, Harry Hengster, R. Krieger, R. Sinković
  Binary Decision Diagrams and Testing
  1993 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
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  Abstract

  Binary Decision Diagrams (BDD's) can be successfully applied to a wide variety of tasks in digital system design, verification and testing. In this paper we focus on the area of testing and demonstrate how two key problems, the computation of signal and fault detection probabilities and the synthesis of testable circuits, can profit from a BDD-based approach.
• Bernd Becker, Rolf Drechsler, Harry Hengster
  Local Circuit Transformations Preserving Robust Path-Delay-Fault Testability
  , issue: 1/93, 1993
• Ralf Hahn, Bernd Becker, Harry Hengster
  The Fault Graph and its Application to Combinational Fault Simulation
  1993 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
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  Abstract

  The fault graph is a data structure to store faults and to manage relations between faults. It allows to exploit these relations for testing purposes and to control the order of faults considered. To demonstrate the effectiveness of the fault graph we developed an algorithm for fault simulation in combinational circuits that is based on this data structure. The algorithm is conceptually simple. Experiments show that it is superior to a sophisticated fanout oriented fault simulation algorithm.
• R. Krieger, Bernd Becker, Harry Hengster
  lgc++: Ein Werkzeug zur Implementierung von Logiken als abstrakte Datentypen in C++
  , 1993