RealTest II — zweite Förderperiode

| project staff | cooperation partners | project description |

Modern nano-electronic circuits and systems are prone to massive parameter variations, which has led to a change of paradigms in design and test of such systems. For instance, systems are designed to be robust, i.e. they are extended by fault-tolerance mechanisms at various levels. Also variation-tolerant, adaptive and self-calibrating systems are gaining in importance. Furthermore, due to the connection between parameter variations and variations of the timing behaviour of components, delay times can no longer be characterised by fixed numbers, but statistical methods are required. As a consequence, classical test tasks, like simulation and test pattern generation, need to be adapted, and also the co-operation of different test tools has to be redesigned such as to reflect the new models. In this project, we work on efficient test methods that cope with the additional challenges posed by statistical and variation-aware design and test.

Example: Due to delay variations in individual gates, a fault is detected by two different test patterns in two different instances of the same circuit (01/11 on the left-hand side, 00/10 on the right-hand side).

In our research, we adapt the most relevant test tools to consider statistical circuit models. In particular, an iterative flow involving statistical fault simulation developed in Stuttgart and efficient test pattern generation developed in Freiburg and Passau has been devised in order to achieve higher fault coverage from a statistical point of view. The statistical characterisation of fault effects under process variations is done based on electrical-level fault modelling performed by the project partners in Dresden. The project partners in Paderborn develop special strategies for adaptive and self-calibrating systems that avoid yield lost and allow a better grading of system robustness.

The following paragraphs describe the sub-project being worked on at the University of Freiburg. For more information on the work done by the other partners, please visit the joint project’s website.

Identification and test of critical components under process variations

One part of our work in this project focuses on the identification of critical components, i.e. components that are more prone to fail under process variations. The complex timing behaviour that arises from process variations, as well as fault-tolerance mechanisms have to be taken account in this analysis. The aim is to specify a criticality metric that reflects the probability that a certain component will fail under process variations. The results of such analysis can be used to guide further robustness-enhancing schemes. This work is complemented by dedicated test pattern generation (ATPG) aimed at producing test patterns for the components that have been identified as critical. In this context, ATPG methods usually have to cope with highly complex and hard-to-solve problem instances that may even impose additional conditions (multi-constraint ATPG). Here, we adapt the SAT-based ATPG-methods that have been developed by our research group for many years.

conference and journal papers (refereed)

• A. Czutro, M. Imhof, J. Jiang, A. Mumtaz, M. Sauer, B. Becker, I. Polian and H.-J.Wunderlich, “Variation-Aware Fault Grading,” in Asian Test Symp., November 2012. 


• M. Sauer, A. Czutro, I. Polian and B. Becker, “Small-Delay-Fault ATPG with Waveform Accuracy,” in Int’l Conf. on CAD, November 2012.


• L. Feiten, M. Sauer, T. Schubert, A. Czutro, E. Böhl, I. Polian and B. Becker, “#SAT-based Vulnerability Analysis of Security Components — A Case Study,” in Int’l Symp. on Defect and Fault Tolerance, October 2012.


• S. Hillebrecht, M. Kochte, H.-J. Wunderlich and B. Becker, “Exact Stuck-at Fault Classification in Presence of Unknowns,” European Test Symp., pp. 98-103, 2012.


• A. Czutro, M. Sauer, T. Schubert, I. Polian and B. Becker, “SAT-ATPG Using Preferences for Improved Detection of Complex Defect Mechanisms,” in VLSI Test Symp., April 2012.


• J. Jiang, M. Sauer, A. Czutro, B. Becker and I. Polian, “On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints,” in Conf. on Design, Automation and Test in Europe, March 2012.


• M. Sauer, J. Jiang, A. Czutro, I. Polian and B. Becker, “Efficient SAT-Based Search for Longest Sensitisable Paths,” in Asian Test Symp., November 2011.


• M. Sauer, A. Czutro, I. Polian and B. Becker, “Estimation of Component Criticality in Early Design Steps,” in IEEE Int’l Online Testing Symp., pp. 104–110, July 2011.


• M. Sauer, A. Czutro, T. Schubert, S. Hillebrecht, I. Polian and B. Becker, “SAT-based Analysis of Sensitisable Paths,” in IEEE Design and Diagnostics of Electronic Circuits and Systems, pp. 93–98, April 2011. Best Paper Award in the Test Category.


• F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren and H.-J. Wunderlich, “Variation-Aware Fault Modeling,” in Asian Test Symp., 2010.


• M. Hunger, S. Hellebrand, A. Czutro, I. Polian and B. Becker, “ATPG-Based Grading of Strong Fault-Secureness,” in IEEE Int’l Online Testing Symp., 2009.

conference and journal papers (invited)

• F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren and H.-J. Wunderlich, “Variation-aware fault modeling,” SCIENCE CHINA Information Sciences, Volume 54, Number 9, pp. 1813-1826, Science China Press and Springer Verlag.


• B. Becker, S. Hellebrand, I. Polian, B. Straube, W.Vermeiren and H.-J. Wunderlich, “Massive Statistical Process Variations — A Grand Challenge for Testing Nanoelectronic Circuits,” in Workshop on Dependable and Secure Nanocomputing, pp. 95-100, 2010.


• I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich and P. Maxwell, “Towards Variation-Aware Test Methods,” in European Test Symp., pp. 219-225, 2011.

workshop papers

• A. Czutro, M. Sauer, I. Polian and B. Becker, “Multi-Conditional ATPG using SAT with Preferences,” in GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, February 2012.


• M. Sauer, S. Kupferschmid, A. Czutro, I. Polian, S.M. Reddy and B. Becker, “Functional Justification in Sequential Circuits using SAT and Craig Interpolation,” in GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, February 2012.


• J. Jiang, M. Sauer, A. Czutro, B. Becker and I. Polian, “On the Optimality of K Longest Path Generation,” in Workshop on RTL and High Level Testing, November 2011.