Funktionale Simulation

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The task of hardware verification is to prove that a given circuit implementation is conform with its specifiction. A popular method of proving that a combinational circuit is equivalent to its specification is to transfer both specification and implementation into a normalform and then check their equality.

In this context Binary Decision Diagrams (BDDs) have proved their value as compact normalform for certain circuit categories, e.g. control logic or adders. For other circuits e.g. multipliers however, the BDD-based approach fails, because the representation of multipliers with BDDs is always of exponential size.

For sequential circuits the proof of equivalence of specification and implementation is also often accomplished with BDD-based methods. Sometimes the sequential circuit is too large, so that it can\'t be dealt with by current automatic verification methods. In this case in practice you still have to be content with simulations, which can help to find design faults. This way it is possible to give at least some certainty that no faults have slipped in during design. In the project \"Functional Simulation\" a method is being devoloped which accelerates simulation and therefore makes it possible to test more simulation-patterns in a given timeframe.

Cycle-based functional simulation is used for validation of very large sequential circuits.
To accelerate functional simulation decision diagrams were used to reduce the operating time of a simulation-cycle (which in the worst case is proportional to the number of logic gates in the circuit in case of event-controlled or compiler-based simulation) to a runtime, which simply is proportional to the number of in- and outputs of the circuit.

This advantage however is negated if the used decision diagrams and therefore the simulation programs are very large so that the access of the program to the memory becomes very slow due to the memory hierarchy. Because of this it is a central problem to limit the required memory.

Our approach tries to avoid large simulation programs with help of specific optimization techniques which minimize the size of decision diagrams and also consider the medium number of operations for analysing an input-vector.