PTL-Synthese mit Multiplexerschaltkreisen

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The basic problem when designing a circuit is to compile a given circuit specification into a correct circuit implementation. A partial stage in this design flow is the logic synthesis, which generates an adequate implementation starting with the specification, which is provided by the functional layout. The result of the logic synthesis is a netlist description using a library of basic cells.

The main topics of this project primarily belongs to the combinational logic synthesis, i.e. the automatic synthesis of combinational partial functions (without registers).

The DD-based logic synthesis tries to use the efficiency of decision diagrams (DDs) when representing and manipulating boolean functions.

In a first attempt the DD-based logic synthesis was used for the automatic generation of Pass Transistor Logic circuits.

Pass Transistor Logic (PTL) turned out to be a competitive alternative to the static CMOS-design (concerning area, delay time and power consumption).

Existing automatic PTL-synthesis tools used a direct illustration of \"decomposed BDDs\" in PTL: Thereby the circuit, which shall be realized in PTL, is divided into cluster and BDDs (Binary Decision Diagrams) are constructed for the partial circuits of every single cluster. The BDD-nodes can be interpreted as multiplexer and can then be realized by transistors in a simple way:



In the current project this approach was improved through the optimization of general multiplexer circuits for the PTL-synthesis. Characteristics of BDDs, which only matter in verification (since they lead to canonical representations), are abandoned here. In comparison with BDDs multiplexer circuits

have no restriction on the variable order

select-inputs of multiplexers can\'t only be connected with primary inputs, but also with internal signals.

The utilization of the arising optimization potential in multiplexer circuits lead to respectable improvements concerning the area and also the depth of the resulting PTL-circuits.