Technologieabhängige Logiksynthese

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project staff
Chair of Computer Architecture
Rolf Drechsler, Prof. Dr.
Wolfgang Günther, Dr.

Logic synthesis deals with all tasks and problems, which have to be managed in connection with an optimal realization of combinational and sequential logic.

Exact Synthesis

An exact method has been developed, which calculates a minimal circuit for a given library (a set of basic gates). To define the functionality of partial functions, BDDs are used to constrain the search domain. The algorithm has been generalized in order to automize and generate ULMs (Universal Logic Modules) optimally.

Technology-based Synthesis

Usually the synthesis-process is split up into several stages:

1. High-level synthesis (compilation into a netlist)
   
2. (technology-independent) Synthesis / Optimization
   
3. Technology mapping ( mapping to manufacturing process)
   
4. Placement / Routing
   

Thereby the optimization is carried out after certain criteria, which don’t necessarily have to be good for the following level. The technology-independent synthesis often minimizes wrt. literals, but when using FPGAs (Field Programmable Gate Arrays) as implementation technology, the amount of literals is usually not a good measure for the size of the resulting circuit. Therefore we are working on a BDD-based approach, which completes technology-independent synthesis and technology mapping in one step. Here, among others,also linearly transfomed BDDs were used.

EXOR-based Synthesis

Because of the common usage of FPGAs, the application of EXOR-gates has become very promising in logic synthesis, since EXOR-gates often create the same costs as AND-/OR-gates in FPGAs. In this connection LT-BDDs can be seen, which use EXOR-Gates at the inputs. This was also done in the technology-based synthesis.

Rolf Drechsler, Prof. Dr., Wolfgang Günther, Dr. Exact Circuit Synthesis Advanced Computer Systems, 1998

Wolfgang Günther, Dr., Rolf Drechsler, Prof. Dr. Creating Hard Problem Instances in Logic Synthesis using Exact Minimization IEEE International Symposium on Circuits and Systems, 1999

Rolf Drechsler, Prof. Dr., Wolfgang Günther, Dr. Generation of Optimal Universal Logic Modules IEEE EUROMICRO Conference, 1999

Wolfgang Günther, Dr., Rolf Drechsler, Prof. Dr. ACTion: Combining Technology Mapping and Logic Synthesis for MUX based FPGAs EUROMICRO, 2000

Wolfgang Günther, Dr., Rolf Drechsler, Prof. Dr. Performance Driven Optimization for MUX based FPGAs VLSI Design Conf., 2001