SHIVA: Sichere Hardware in der Informationsverarbeitung

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2019

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• Benjamin Thiemann, Linus Feiten, Pascal Raiola, Bernd Becker, Matthias Sauer
  On Integrating Lightweight Encryption in Reconfigurable Scan Networks
  2019 IEEE European Test Symposium
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  Abstract

  Reconfigurable Scan Networks (RSNs) are a powerful tool for testing and maintenance of embedded systems, since they allow for flexible access to on-chip instrumentation such as built-in self-test and debug modules. The deployment of RSNs, however, can be exploited by malicious users as a side-channel in order to gain information about sensitive data or intellectual property and to recover secret keys. Hence, implementing appropriate countermeasures to secure the access to and data integrity of embedded instrumentation is of high importance. In this paper we present a novel hardware and software combined approach to ensure data privacy in IEEE Std 1687 (IJTAG) RSNs. To do so, both a secure IJTAG compliant plug-and-play instrument wrapper and a versatile software toolchain are introduced. The wrapper demonstrates the necessary architectural adaptations required when using a lightweight stream cipher, whereas the software toolchain provides a seamless integration of the testing workflow with stream cipher. The applicability of the method is demonstrated by an FPGA-based implementation. We report on the performance of the developed instrument wrapper, which is empirically shown to have only a small impact on the workflow in terms of hardware overhead, operational costs and test time overhead.
• Pascal Raiola, Benjamin Thiemann, Jan Burchard, Ahmed Atteya, Natalia Kapstova, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer
  On Secure Data Flow in Reconfigurable Scan Networks
  2019 Conf. on Design, Automation and Test in Europe

2018

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• Pascal Raiola, Michael A. Kochte, Ahmed Atteya, Laura Rodríguez Gómez, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer
  Detecting and Resolving Security Violations in Reconfigurable Scan Networks
  2018 IEEE International Symposium on On-Line Testing and Robust System Design
• Ahmed Atteya, Michael Kochte, Matthias Sauer, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
  Online Prevention of Security Violations in Reconfigurable Scan Networks
  2018 IEEE European Test Symposium
• Pascal Raiola, Michael A. Kochte, Ahmed Atteya, Laura Rodríguez Gómez, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer
  Design of Reconfigurable Scan Networks for Secure Data Transmission
  2018 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”

2017

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• Michael A. Kochte, Matthias Sauer, Laura Rodríguez Gómez, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
  Specification and verification of security in reconfigurable scan networks
  2017 IEEE European Test Symposium
• Matthias Sauer, Pascal Raiola, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian
  Sensitized Path PUF: A Lightweight Embedded Physical Unclonable Function
  2017 Conf. on Design, Automation and Test in Europe
• Michael Kochte, Sauer M, Laura Rodriguez Gomez, Raiola P, Becker B, Hans-Joachim Wunderlich
  Specification and verification of security in reconfigurable scan networks
  2017 IEEE European Test Symposium

2016

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• Mathias Soeken, Pascal Raiola, Baruch Sterin, Bernd Becker, Giovanni De Micheli, Matthias Sauer
  SAT-based Combinational and Sequential Dependency Computation
  2016 Haifa Verification Conference (HVC)
• Mathias Soeken, Pascal Raiola, Baruch Sterin, Matthias Sauer
  SAT-based Functional Dependency Computation
  2016 International Workshop on Logic & Synthesis
• Michael Kochte, Rafal Baranowski, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich
  Formal Verification of Secure Reconfigurable Scan Network Infrastructure
  2016 IEEE European Test Symposium
• Michael Kochte, Matthias Sauer, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
  SHIVA: Sichere Hardware in der Informationsverarbeitung Formaler Nachweis komplexer Sicherheitseigenschaften in rekonfigurierbarer Infrastruktur
  2016 eda Workshop
• Linus Feiten, Jonathan Oesterle, Tobias Martin, Matthias Sauer, Bernd Becker
  Systematic Frequency Biases in Ring Oscillator PUFs on FPGAs
  2016 IEEE Transactions on Multi-Scale Computing Systems (TMSCS), volume: PP, issue: 99
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  Abstract

  Physically unclonable functions (PUFs) are an emerging primitive in hardware security, enabling the identification of computer-chips. A promising type particularly for FPGA implementations is the Ring Oscillator (RO) PUF, where signal delays – stemming from uncontrollable variations in the manufacturing process – are used as device-specific characteristics. Based on experimental results gathered with 38 identical Altera FPGAs, we show the existence of nondevice- specific i.e. systemic RO frequency biases, traced back to (1) the internal routing within the RO’s look-up tables, (2) the RO locations on the FPGAs, or (3) the non-PUF payload activity. As these biases are the same for all devices, the result is poor inter-device uniqueness and unreliable signatures under changing payloads. After characterising these biases with a newly developed set of metrics, we suggest a method to overcome them: Using only a small sample of devices, the average bias over all devices for each RO is predicted and the relative differences caused by systemic biases are nullified. We demonstrate the viability of this method by determining the sufficient random sample sizes and showing that the inter-device uniqueness is drastically increased and the PUF signatures become reliable even under changing payload activities.