2021

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• Tobias Paxian, Pascal Raiola, Bernd Becker
  On Preprocessing for Weighted MaxSAT
  2021 VMCAI - 22nd International Conference on Verification, Model Checking, and Abstract Interpretation, Springer, Band: 12597, Seiten: 556 - 577
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  Kurzfassung

  Both techniques can be used by all MaxSAT solvers, though our focus lies on Pseudo Boolean constraint based MaxSAT solvers. Experimental results show the effectiveness of both techniques on a large set of benchmarks from a hardware security application and from the 2019 MaxSAT Evaluation. In particular for the hardest of the application benchmarks, the solver Pacose with GBMO and TrimMaxSAT performs best compared to the MaxSAT Evaluation solvers of 2019. For the benchmarks of the 2019 MaxSAT Evaluation, we show that with the proposed techniques the top solver combination solves significantly more instances.

2020

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• Pascal Raiola, Tobias Paxian, Bernd Becker
  Minimal Witnesses for Security Weaknesses in Reconfigurable Scan Networks
  2020 IEEE European Test Symposium
• Pascal Raiola, Tobias Paxian, Bernd Becker
  Partial (un-) weighted MaxSAT benchmarks: minimizing witnesses for security weaknesses in reconfigurable scan networks
  2020 MaxSAT Evaluation 2020, Band: 14, Seiten: 44 - 44

2019

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• Benjamin Thiemann, Linus Feiten, Pascal Raiola, Bernd Becker, Matthias Sauer
  On Integrating Lightweight Encryption in Reconfigurable Scan Networks
  2019 IEEE European Test Symposium
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  Kurzfassung

  The applicability of the method is demonstrated by an FPGA-based implementation. We report on the performance of the developed instrument wrapper, which is empirically shown to have only a small impact on the workflow in terms of hardware overhead, operational costs and test time overhead.
• Pascal Raiola, Benjamin Thiemann, Jan Burchard, Ahmed Atteya, Natalia Kapstova, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer
  On Secure Data Flow in Reconfigurable Scan Networks
  2019 Conf. on Design, Automation and Test in Europe

2018

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• Pascal Raiola, Michael A. Kochte, Ahmed Atteya, Laura Rodríguez Gómez, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer
  Detecting and Resolving Security Violations in Reconfigurable Scan Networks
  2018 IEEE International Symposium on On-Line Testing and Robust System Design
• Ahmed Atteya, Michael Kochte, Matthias Sauer, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
  Online Prevention of Security Violations in Reconfigurable Scan Networks
  2018 IEEE European Test Symposium
• Felix Neubauer, Jan Burchard, Pascal Raiola, Jochen Rivoir, Bernd Becker, Matthias Sauer
  Efficient Generation of Parametric Test Conditions for AMS Chips with an Interval Constraint Solver
  2018 IEEE VLSI Test Symposium (VTS'18)
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  Kurzfassung

  The characterization of analog-mixed signal (AMS) silicon requires a suitable pattern set able to exercise the parametric operational space to – among other tasks – validate the correct (specified) working behaviour of the device under test. As experience shows, most of the unexpected problems occur for very specific value combinations of a few test condition variables that were not expected to have an influence. Additionally, restrictions on the operational conditions have to be taken into account. We present a method to efficiently create a set of test conditions to cover such a constrained search space with a user-defined density. First, an initial test condition set is generated using quasirandom Sobol sequences. Secondly, we analyse the test conditions to identify and fill uncovered areas in the parameter space using the in-house interval constraint solver iSAT3. The applicability of the method is demonstrated by experimental results on a 19-dimensional search space using a realistic set of constraints.
• Felix Neubauer, Jan Burchard, Pascal Raiola, Jochen Rivoir, Bernd Becker, Matthias Sauer
  High-Coverage AMS Test Space Optimization by Efficient Parametric Test Condition Generation
  2018 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
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  Kurzfassung

  The characterization of analog-mixed signal (AMS) silicon requires a suitable pattern set able to exercise the parametric operational space to – among other tasks – validate the correct (specified) working behaviour of the device under test. As experience shows, most of the unexpected problems occur for very specific value combinations of a few test condition variables that were not expected to have an influence. Additionally, restrictions on the operational conditions have to be taken into account. We present a method to efficiently create a set of test conditions to cover such a constrained search space with a user-defined density. First, an initial test condition set is generated using quasirandom Sobol sequences. Secondly, we analyse the test conditions to identify and fill uncovered areas in the parameter space using the in-house interval constraint solver iSAT3. The applicability of the method is demonstrated by experimental results on a 19-dimensional search space using a realistic set of constraints.
• Pascal Raiola, Michael A. Kochte, Ahmed Atteya, Laura Rodríguez Gómez, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer
  Design of Reconfigurable Scan Networks for Secure Data Transmission
  2018 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”

2017

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• Michael A. Kochte, Matthias Sauer, Laura Rodríguez Gómez, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
  Specification and verification of security in reconfigurable scan networks
  2017 IEEE European Test Symposium
• Jan Burchard, Felix Neubauer, Pascal Raiola, Dominik Erb, Bernd Becker
  Evaluating the Effectiveness of D-Chains in SAT based ATPG
  2017 IEEE Latin American Test Symposium (LATS'17)
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  Kurzfassung

  With the ever increasing size of today’s Very-Large-Scale-Integration (VLSI) designs new approaches for test pattern generation become more and more popular. One of the best known methods is SAT-based automatic test pattern generation (ATPG) which, in contrast to classical structural ATPG, first generates a mathematical representation of the problem in form of a Boolean formula. A specialized solver evaluates this representation to determine the testability of faults and extracts a test pattern in case a satisfying assignment was found. In order to increase the solving speed introduced the concept of D-chains which add additional information to the mathematical model. In return, this forces the solver to only consider assignments that might lead to a valid test pattern and thus reduce the search space. With the advent of incremental solving new concepts like the backward D-chain or even more recently an indirect D-chain were introduced. However, none of the previous publications tried to analyze and evaluate which of these methods is the most beneficial. In this paper we present a thorough investigation of the different D-chain concepts to evaluate which is the best method for different problems. In addition, we propose a new indirect D-chain algorithm with two extensions. Our experimental results show that depending on the incorporated D-chain the runtime can be reduced tremendously.
• Matthias Sauer, Pascal Raiola, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian
  Sensitized Path PUF: A Lightweight Embedded Physical Unclonable Function
  2017 Conf. on Design, Automation and Test in Europe
• Pascal Raiola, Dominik Erb, Sudhakar Reddy, Bernd Becker
  Accurate Diagnosis of Interconnect Open Defects based on the Robust Enhanced Aggressor Victim Model
  2017 30th International Conference on VLSI Design
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  Kurzfassung

  In addition, it allows to distinguish faults at the same interconnect and thus reducing the area that has to be considered for physical failure analysis. Experimental results show the high efficiency of the new method handling circuits with up to 500,000 non-equivalent faults and considerably increasing the diagnostic resolution.
• Pascal Raiola, Jan Burchard, Felix Neubauer, Dominik Erb, Bernd Becker
  Evaluating the Effectiveness of D-chains in SAT-based ATPG and Diagnostic TPG
  2017 J Electron Test, Band: 33, Nummer: 6, Seiten: 751 - 767
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  Kurzfassung

  The ever increasing size and complexity of today’s Very-Large-Scale-Integration (VLSI) designs requires a thorough investigation of new approaches for the generation of test patterns for both test and diagnosis of faults. SAT-based automatic test pattern generation (ATPG) is one of the most popular methods, where, in contrast to classical structural ATPG methods, first a mathematical representation of the problem in form of a Boolean formula is generated, which is then evaluated by a specialized solver. If the considered fault is testable, the solver will return a satisfying assignment, from which a test pattern can be extracted; otherwise no such assignment can exist. In order to speed up test pattern generation, the concept of D-chains was introduced by several researchers. Thereby supplementary clauses are added to the Boolean formula, reducing the search space and guiding the solver toward the solution. In the past, different variants of D-chains have been developed, such as the backward D-chain or the indirect D-chain. In this work we perform a thorough analysis and evaluation of the D-chain variants for test pattern generation and also analyze the impact of different D-chain encodings on diagnostic test pattern generation. Our experimental results show that depending on the incorporated D-chain the runtime can be reduced tremendously.

2016

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• Mathias Soeken, Pascal Raiola, Baruch Sterin, Bernd Becker, Giovanni De Micheli, Matthias Sauer
  SAT-based Combinational and Sequential Dependency Computation
  2016 Haifa Verification Conference (HVC)
• Mathias Soeken, Pascal Raiola, Baruch Sterin, Matthias Sauer
  SAT-based Functional Dependency Computation
  2016 Synthesis
• Michael Kochte, Matthias Sauer, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
  Formaler Nachweis komplexer Sicherheitseigenschaften in rekonfigurierbarer Infrastruktur
  2016 eda Workshop