Liste filtern: Jahre: 2017
2016 | alle anzeigen nach oben zur Jahresübersicht Matthias Sauer, Pascal Raiola, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian Sensitized Path PUF: A Lightweight Embedded Physical Unclonable Function 2017 Conf. on Design, Automation and Test in Europe Pascal Raiola, Dominik Erb, Sudhakar Reddy, Bernd Becker Accurate Diagnosis of Interconnect Open Defects based on the Robust Enhanced Aggressor Victim Model 2017 30th International Conference on VLSI Design Interconnect opens are known to be one of the predominant defects in nanoscale technologies. Automatic test pattern generation for open faults is challenging, because of their rather unstable behavior and the numerous electrical parameters which need to be considered. Thus, most approaches try to avoid accurate modeling of all constraints like the influence of the aggressors on the open net and use simplified fault models in order to detect as many faults as possible or make assumptions which decrease both complexity and accuracy. Yet, this leads to the problem that not only generated tests may be invalidated but also the localization of a specific fault may fail -- in case such a model is used as basis for diagnosis. Furthermore, most of the models do not consider the problem of oscillating behavior, caused by feedback introduced by coupling capacitances, which occurs in almost all designs.
The Robust Enhanced Aggressor Victim Model (REAV) does not only consider the influence of all aggressors accurately but also guarantees robustness against oscillating behavior as well as process variations affecting the thresholds of gates driven by an open interconnect.
In this work we present the first diagnostic classification algorithm for this model. This algorithm considers all constraints enforced by the REAV model accurately - and hence handles unknown values as well as oscillating behavior.
In addition, it allows to distinguish faults at the same interconnect and thus reducing the area that has to be considered for physical failure analysis. Experimental results show the high efficiency of the new method handling circuits with up to 500,000 non-equivalent faults and considerably increasing the diagnostic resolution. Kurzfassung Jan Burchard, Felix Neubauer, Pascal Raiola, Dominik Erb, Bernd Becker Evaluating the Effectiveness of D-Chains in SAT based ATPG 2017 IEEE Latin American Test Symposium (LATS'17) nach oben zur Jahresübersicht Mathias Soeken, Pascal Raiola, Baruch Sterin, Bernd Becker, Giovanni De Micheli, Matthias Sauer SAT-based Combinational and Sequential Dependency Computation 2016 Haifa Verification Conference (HVC) Mathias Soeken, Pascal Raiola, Baruch Sterin, Matthias Sauer SAT-based Functional Dependency Computation 2016 International Workshop on Logic & Synthesis Michael Kochte, Matthias Sauer, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich SHIVA: Sichere Hardware in der Informationsverarbeitung
Formaler Nachweis komplexer Sicherheitseigenschaften in rekonfigurierbarer Infrastruktur
2016 eda Workshop