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Name Matthias Sauer, Dr. Matthias Sauer, Dr.
Adresse Technische Fakultät Albert-Ludwigs-Universität Georges Köhler Allee, Gebäude 51 79110 Freiburg im Breisgau Deutschland
Büro Gebäude 51, Raum 01..031
Telefon ++49 +761 203-8143
eMail sauerm@informatik.uni-freiburg.de

Matthias Sauer

Jahre: 2017 | 2016 | 2015 | 2014 | 2013 | 2012 | 2011

    2017

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    • Matthias Sauer, Pascal Raiola, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian
      Sensitized Path PUF: A Lightweight Embedded Physical Unclonable Function
      2017 Conf. on Design, Automation and Test in Europe
    • Linus Feiten, Matthias Sauer, Bernd Becker
      Implementation of Delay-Based PUFs on Altera FPGAs
      In: Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment
      2017, Springer International Publishing, Seiten: 211 - 235, ISBN: 978-3-319-44318-8

    2016

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    • Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian
      On Optimal Power-aware Path Sensitization
      2016 2016 25nd IEEE Asian Test Symposium (ATS)
    • Mathias Soeken, Pascal Raiola, Baruch Sterin, Bernd Becker, Giovanni De Micheli, Matthias Sauer
      SAT-based Combinational and Sequential Dependency Computation
      2016 Haifa Verification Conference (HVC)
    • Mathias Soeken, Pascal Raiola, Baruch Sterin, Matthias Sauer
      SAT-based Functional Dependency Computation
      2016 International Workshop on Logic & Synthesis
    • Michael Kochte, Rafal Baranowski, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich
      Formal Verification of Secure Reconfigurable Scan Network Infrastructure
      2016 IEEE European Test Symposium
    • Michael Kochte, Matthias Sauer, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
      SHIVA: Sichere Hardware in der Informationsverarbeitung Formaler Nachweis komplexer Sicherheitseigenschaften in rekonfigurierbarer Infrastruktur
      2016 eda Workshop
    • Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
      Effective Generation and Evaluation of Diagnostic SBST Programs
      2016 IEEE VLSI Test Symposium
    • Linus Feiten, Matthias Sauer, Bernd Becker
      On Metrics to Quantify the Inter-Device Uniqueness of PUFs
      2016 TRUDEVICE Workshop, Dresden
    • Matthias Sauer, Sven Reimer, Daniel Tille, Karsten Scheibler, Dominik Erb, Ulrike Pfannkuchen, Bernd Becker
      Clock Cycle Aware Encoding for SAT-based Circuit Initialization
      2016 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
      Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns
      2016 21st Asia and South Pacific Design Automation Conference
    • Linus Feiten, Jonathan Oesterle, Tobias Martin, Matthias Sauer, Bernd Becker
      Systematic Frequency Biases in Ring Oscillator PUFs on FPGAs
      2016 IEEE Transactions on Multi-Scale Computing Systems (TMSCS), Band: PP, Nummer: 99
    • Matthias Sauer, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian
      Utilizing Intrinsic Delay Variability in Complex Digital Circuits for Defining PUF Behavior
      2016 TRUDEVICE Workshop, Dresden

    2015

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    • Linus Feiten, Tobias Martin, Matthias Sauer, Bernd Becker
      Improving RO-PUF Quality on FPGAs by Incorporating Design-Dependent Frequency Biases
      2015 IEEE European Test Symposium
    • Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
      Identification of High Power Consuming Areas with Gate Type and Logic Level Information
      2015 IEEE European Test Symposium
    • Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
      On the Automatic Generation of SBST Test Programs for In-Field Test
      2015 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Dominik Erb, Michael A. Kochte, Sven Reimer, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
      Accurate QBF-based Test Pattern Generation in Presence of Unknown Values
      2015 Computer-Aided Design of Integrated Circuits and Systems (TCAD)
    • Linus Feiten, Tobias Martin, Matthias Sauer, Bernd Becker
      Analysis and utilisation of deviations in RO-PUFs under altered FPGA designs
      2015 TRUDEVICE Workshop, Grenoble
    • Linus Feiten, Matthias Sauer
      Extracting the RC4 secret key of the Open Smart Grid Protocol (OSGP)
      2015 Industrial Control System Security (ICSS) Workshop
    • Linus Feiten, Matthias Sauer, Tobias Schubert, Victor Tomashevich, Ilia Polian, Bernd Becker
      Formal Vulnerability Analysis of Security Components
      2015 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Band: 34, Nummer: 8, Seiten: 1358 - 1369
    • Andreas Riefert, Matthias Sauer, Sudhakar Reddy, Bernd Becker
      Improving Diagnosis Resolution of a Fault Detection Test Set
      2015 VLSI Test Symposium
    • Bernd Becker, Matthias Sauer, Christoph Scholl, Ralf Wimmer
      Modeling Unknown Values in Test and Verification
      In: Formal Modeling and Verification of Cyber-Physical Systems (Proceedings of the 1st International Summer School on Methods and Tools for the Design of Digital Systems)
      2015, Springer, Rolf Drechsler, Ulrich Kühne, Seiten: 122 - 150, Rolf Drechsler, Ulrich Kühne, ISBN: 978-3-658-09993-0
    • Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
      Multi-Cycle Circuit Parameter Independent ATPG for Interconnect Open Defects
      2015 33rd VLSI Test Symposium (VTS)
    • Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
      On the Automatic Generation of SBST Test Programs for In-Field Test
      2015 Conf. on Design, Automation and Test in Europe
    • Matthias Sauer, Bernd Becker, Ilia Polian
      PHAETON: A SAT-based Framework for Timing-aware Path Sensitization
      2015 Ieee T Comput, Band: PP, Nummer: 99
    • Karina Gitina, Ralf Wimmer, Sven Reimer, Matthias Sauer, Christoph Scholl, Bernd Becker
      Solving DQBF Through Quantifier Elimination
      2015 Conf. on Design, Automation and Test in Europe

    2014

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    • Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
      Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects
      2014 23nd IEEE Asian Test Symposium (ATS)
    • Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker
      Incremental Encoding and Solving of Cardinality Constraints
      2014 International Symposium on Automated Technology for Verification and Analysis, Springer International Publishing, Band: 8837, Seiten: 297 - 313
    • Sven Reimer, Matthias Sauer, Paolo Marin, Bernd Becker
      QBF with Soft Variables
      2014 International Workshop on Automated Verification of Critical Systems (AVOCS)
    • Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer
      Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization
      2014 International Conference on Design Technology of Integrated Systems In Nanoscale Era (DTIS)
    • Matthias Sauer, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker
      Variation-Aware Deterministic ATPG
      2014 IEEE European Test Symposium , Seiten: 1 - 6
    • Matthias Sauer, Sven Reimer, Sudhakar M. Reddy, Bernd Becker
      Efficient SAT-based Circuit Initialization for Large Designs
      2014 Int'l Conf. on VLSI Design
    • Andreas Riefert, Lyl Ciganda, Matthias Sauer, Paolo Bernadi, Matteo Sonza Reorda, Bernd Becker
      An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults
      2014 Conf. on Design, Automation and Test in Europe
    • Dominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker
      Efficient SMT-based ATPG for Interconnect Open Defects
      2014 Conf. on Design, Automation and Test in Europe
    • Dominik Erb, Michael Koche, Matthias Sauer, Stefan Hillebrecht, Tobias Schubert, Hans-Joachim Wunderlich, Bernd Becker
      Exact Logic and Fault Simulation in Presence of Unknowns
      2014 ACM Transactions on Design Automation of Electronic Systems (TODAES), Band: 19, Seiten: 28:1 - 28:17
    • Linus Feiten, Andreas Spilla, Matthias Sauer, Tobias Schubert, Bernd Becker
      Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs
      2014 Information Security Journal: A Global Perspective, Band: 22, Nummer: 5-6, Seiten: 265 - 273
    • Dominik Erb, Karsten Scheibler, Michael Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
      Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic
      2014 Int'l Test Conf.
    • Der Andere Verlag, Seite: 184
      Testing Time - Time to Test? -- Using Formal Methods for the Timing Analysis of Digital Circuits --
      ISBN: 978-3-86247-451-6
      Matthias Sauer
    • Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker
      Using MaxBMC for Pareto-Optimal Circuit Initialization
      2014 Conf. on Design, Automation and Test in Europe

    2013

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    • Tobias Schubert, Jan Burchard, Matthias Sauer, Bernd Becker
      S-Trike: A Mobile Robot Platform for Higher Education
      2013 International Conference on Computer Applications in Industry and Engineering, Seiten: 243 - 248
    • Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Victor Tomashevich, Eberhard Böhl, Ilia Polian, Bernd Becker
      #SAT for Vulnerability Analysis of Security Components
      2013 (Workshop-Paper, Informal Proceedings) IEEE European Test Symposium
    • Benjamin Andres, Matthias Sauer, Martin Gebser, Tobias Schubert, Bernd Becker, Torsten Schaub
      Accurate Computation of Sensitizable Paths using Answer Set Programming
      2013 Int. Conf. on Logic Programming and Nonmonotonic Reasoning, Seiten: 92 - 101
    • Dominik Erb, Michael A Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
      Accurate Multi-Cycle ATPG in Presence of X-Values
      2013 22nd IEEE Asian Test Symposium (ATS)
    • Linus Feiten, Andreas Spilla, Matthias Sauer, Tobias Schubert, Bernd Becker
      Analysis of Ring Oscillator PUFs on 60nm FPGAs
      2013 TRUDEVICE Workshop, Avignon
    • Matthias Sauer, Sven Reimer, Stefan Kupferschmid, Tobias Schubert, Paolo Marin, Bernd Becker
      Applying BMC, Craig Interpolation and MAX-SAT to Functional Justification in Sequential Circuits
      2013 RCRA International Workshop on Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion
    • Karsten Scheibler, Matthias Sauer, Kohei Miyase, Bernd Becker
      Controlling Small-Delay Test Power Consumption using Satisfibility Modulo Theory Solving
      2013 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Matthias Sauer, Bernd Becker, Subhasish Mitra
      Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics
      2013 Custom Integrated Circuits Conference, Seiten: 1 - 4
    • Matthias Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung-Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra, Bernd Becker
      Early-Life-Failure Detection using SAT-based ATPG
      2013 Int'l Test Conf., Seiten: 1 - 10
    • Matthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker
      Efficient SAT-Based Dynamic Compaction and Relaxation for Longest Sensitizable Paths
      2013 Conf. on Design, Automation and Test in Europe, Seiten: 448 - 453
    • Karina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker
      Equivalence Checking for Partial Implementations Revisited
      2013 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Universität Rostock ITMZ, Seiten: 61 - 70
    • Karina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker
      Equivalence Checking of Partial Designs using Dependency Quantified Boolean Formulae
      2013 Int'l Conf. on Computer Design, IEEE Computer Society, Seiten: 396 - 403
    • Andreas Riefert, Joerg Mueller, Matthias Sauer, Wolfram Burgard, Bernd Becker
      Identification of Critical Variables using an FPGA-based Fault Injection Framework
      2013 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Andreas Riefert, Joerg Mueller, Matthias Sauer, Wolfram Burgard, Bernd Becker
      Identification of Critical Variables using an FPGA-based Fault Injection Framework
      2013 VLSI Test Symp., Seiten: 1 - 6
    • Matthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker
      Provably Optimal Test Cube Generation Using Quantified Boolean Formula Solving
      2013 ASP Design Automation Conf.
    • Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker
      SAT-based Analysis of Sensitisable Paths
      2013 IEEE Design & Test of Computers, Band: 30, Nummer: 4, Seiten: 81 - 88
    • Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
      Search Space Reduction for Low-Power Test Generation
      2013 22nd IEEE Asian Test Symposium (ATS)
    • Matthias Sauer, Jan Burchard, Tobias Schubert, Ilia Polian, Bernd Becker
      Waveform-Guided Fault Injection by Clock Manipulation
      2013 TRUDEVICE Workshop

    2012

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    • Alexander Czutro, Michael Imhof, Jie Jiang, Abdullah Mumtaz, Matthias Sauer, Bernd Becker, Ilia Polian, Hans-Joachim Wunderlich
      Variation-Aware Fault Grading
      2012 IEEE Asian Test Symp., Seiten: 344 - 349
    • Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Eberhard Böhl, Ilia Polian, Bernd Becker
      #SAT-Based Vulnerability Analysis of Security Components -- A Case Study
      2012 IEEE International Symposium on Defect and Fault Tolerance (DFT), Seiten: 49 - 54
    • Benjamin Andres, Matthias Sauer, Martin Gebser, Tobias Schubert, Bernd Becker, Torsten Schaub
      Accurate Computation of Longest Sensitizable Paths using Answer Set Programming
      2012 GMM/ITG-Fachtagung “Zuverlässigkeit und Entwurf”
    • Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Sudhakar M. Reddy, Bernd Becker
      Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation
      2012 Int'l Conf. on VLSI Design
    • Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
      Functional Justification in Sequential Circuits using SAT and Craig Interpolation
      2012 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
      Functional Test of Small-Delay Faults using SAT and Craig Interpolation
      2012 Int'l Test Conf., Seiten: 1 - 8
    • Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker
      Multi-Conditional ATPG using SAT with Preferences
      2012 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker
      Multi-Conditional SAT-ATPG for Power-Droop Testing
      2012 IEEE European Test Symp.
    • Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
      On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints
      2012 Conf. on Design, Automation and Test in Europe, Seiten: 418 - 423
    • Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
      On the Quality of Test Vectors for Post-Silicon Characterization
      2012 IEEE European Test Symp.
    • Alexander Czutro, Matthias Sauer, Tobias Schubert, Ilia Polian, Bernd Becker
      SAT-ATPG Using Preferences for Improved Detection of Complex Defect Mechanisms
      2012 VLSI Test Symp.
    • Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker
      Small-Delay-Fault ATPG with Waveform Accuracy
      2012 Int'l Conf. on CAD, Seiten: 30 - 36

    2011

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    • Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
      On the Optimality of K Longest Path Generation
      2011 Workshop on RTL and High Level Testing
    • Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker
      Estimation of Component Criticality in Early Design Steps
      2011 IEEE Int'l Online Testing Symp., Seiten: 104 - 110
    • Matthias Sauer, Victor Tomashevich, Jörg Müller, Matthew Lewis, Ilia Polian, Bernd Becker, Wolfram Burgard
      An FPGA-Based Framework for Run-time Injection and Analysis of Soft Errors in Microprocessors
      2011 IEEE Int'l Online Testing Symp., Seiten: 182 - 185
    • Matthias Sauer, Jie Jiang, Alexander Czutro, Ilia Polian, Bernd Becker
      Efficient SAT-Based Search for Longest Sensitisable Paths
      2011 Test Symposium (ATS), 2011 20th Asian, Seiten: 108 - 113
    • Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker
      SAT-Based Analysis of Sensitisable Paths
      2011 IEEE Design and Diagnostics of Electronic Circuits and Systems, Seiten: 93 - 98