2008

 nach oben zur Jahresübersicht

• Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
  Automatic Test Pattern Generation for Interconnect Open Defects
  2008 VLSI Test Symp., Seiten: 181 - 186
• Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
  Automatic Test Pattern Generation for Interconnect Open Defects
  2008 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
• Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
  Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model
  2008 Int'l Test Conf., Seiten: 1 - 10

2003

 nach oben zur Jahresübersicht

• Martin Keim, M. Martin, Bernd Becker, Rolf Drechsler, Paul Molitor
  Polynomial Formal Verification of Multipliers
  2003 Formal Methods in System Design, Band: 22, Nummer: 1, Seiten: 39 - 58

2002

 nach oben zur Jahresübersicht

• Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker
  Sequential n-Detection Criteria: Keep It Simple!
  2002 IEEE Int'l Online Testing Workshop, Seiten: 189 - 190
  » Kurzfassung anzeigen« Kurzfassung verbergen
  Kurzfassung

  The idea of n-detection is to exposure a target fault in n different ways. To denote several detections as `sufficiently different', formal criteria seem to be necessary. In this article, we study the properties of test sequences with respect to four new criteria, which we call difference types. We try to guide the n-detection test sequence generation process for stuck-at faults by difference types and evaluate coverage of a Surprisingly, we have found out that the effectiveness in detecting non-target faults is not affected beyond statistical noise. In our opinion this result underlines the effectiveness of n-detection without sophisticated differentiation criteria.

2000

 nach oben zur Jahresübersicht

• Piet Engelke, Bernd Becker, Martin Keim
  A Parameterizable Fault Simulator for Bridging Faults
  2000 European Test Workshop, Seiten: 63 - 68
• Martin Keim, Piet Engelke, Bernd Becker
  A Parameterizable Fault Simulator for Bridging Faults
  2000 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”

1999

 nach oben zur Jahresübersicht

• Martin Keim, Ilia Polian, Harry Hengster, Bernd Becker
  A Scalable BIST Architecture for Delay Faults
  1999 European Test Workshop, Seiten: 98 - 103
  » Kurzfassung anzeigen« Kurzfassung verbergen
  Kurzfassung

  In this paper we present a scalable BIST (Built-In Self Test) architecture that provides a tunable trade-off between on-chip area demand and test execution time for delay fault testing. So, the architecture can meet test execution time requirements or available area requirements or any target in between. Experiments show the scalability of our approach, e.g. that considerably shorter test execution time can be achieved by storing only a few additional input vectors of the BIST architecture. The gain of test execution time possible with the proposed method ranges from a factor of 2 up to a factor of more than 800000.
• Martin Keim, Nicole Drechsler, Bernd Becker
  Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
  1999 ASP Design Automation Conf., Seiten: 315 - 318
• Bernd Becker, Martin Keim, R. Krieger
  Hybrid Fault Simulation for Synchronous Sequential Circuit
  1999 Jour. Electronic Testing, Band: 3, Seiten: 219 - 238

1998

 nach oben zur Jahresübersicht

• Martin Keim, Nicole Göckel, Rolf Drechsler, Bernd Becker
  Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
  , Nummer: 105/98, 1998
  » Kurzfassung anzeigen« Kurzfassung verbergen
  Kurzfassung

  A symbolic fault simulator is integrated in a Genetic Algorithm (GA) environment to perform {Automatic Test Pattern Generation} (ATPG) for synchronous sequential circuits. In a two phase algorithm test length and fault coverage as well are optimized. However, there are circuits, that are hard to test using random pattern sequences, even if these sequences are genetically optimized. Thus, deterministic aspects are included in the GA environment to improve fault coverage. Experiments demonstrate that both a priori time consuming strategies can be combined at reasonable costs: Tests with higher fault coverages and considerably shorter test sequences than previously presented approaches are obtained.
• Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
  Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
  1998 European Test Workshop, Seiten: 141 - 142
• Martin Keim, Bernd Becker
  Nearly Exact Signal Probabilities for Synchronous Sequential Circuits - An Experimental Analysis
  , Nummer: 106/98, 1998
  » Kurzfassung anzeigen« Kurzfassung verbergen
  Kurzfassung

  In this article we present a strategy how to estimate the signal probabilities for synchronous sequential circuits. For each line in the circuit an OBDDs is constructed only once. Using this OBDD the signal probabilities in every succeeding time frame is computed. We investigated a large set of the ISCAS'89 benchmark circuits, showing that the proposed strategy estimates 75 percent of all signals considered with a relative error of only 10 percent or less.
• Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
  Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm
  1998 Int'l Symp. on Multi-Valued Logic, Seiten: 215 - 220
• Martin Keim, Nicole Göckel, Rolf Drechsler, Bernd Becker
  Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm
  1998 Int'l Symp. on Multi-Valued Logic

1997

 nach oben zur Jahresübersicht

• Nicole Göckel, Martin Keim, Rolf Drechsler, Bernd Becker
  A Genetic Algorithm for Sequential Circuit Test Generation based on Symbolic Fault Simulation
  1997 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
  » Kurzfassung anzeigen« Kurzfassung verbergen
  Kurzfassung

  We present a Genetic Algorithm (GA) for sequential circuit test generation. A Binary Decision Diagram (BDD) based fault simulator, i.e. a fault simulator that uses symbolic methods, is integrated in the GA environment. The fault simulator is used as a more accurate evaluation method. Experiments show that we can generate test patterns for circuits where all previously presented GA approaches fail. Additionally, we reduce the length of the test sequences. A comparison to the pure GA based approach shows the efficiency of this method.
• Nicole Göckel, Martin Keim, Rolf Drechsler, Bernd Becker
  A Genetic Algorithm for Sequential Circuit Test Generation based on Symbolic Fault Simulation
  1997 European Test Workshop
• Rolf Drechsler, Martin Keim, Bernd Becker
  Fault Simulation in Sequential Multi-Valued Logic Networks
  1997 Int'l Symp. on Multi-Valued Logic, Seiten: 145 - 150
  » Kurzfassung anzeigen« Kurzfassung verbergen
  Kurzfassung

  In this paper we present a fault simulator for Sequential Multi-Valued Logic Networks (SMVLN). With this tool we investigate their Random Pattern Testability (RPT). We discuss a unified approach for fault models in SMVLNs and show, that it is possible to describe all static fault models with a global formalism. A large set of experimental results is given that demonstrates the efficiency of our approach. For the first time fault coverages for the Stuck-At Fault Model (SAFM) and Skew Fault Model (SKFM) for large sequential circuits are reported.
• C. Ökmen, Martin Keim, R. Krieger, Bernd Becker
  On Optimizing BIST Architecture by Using OBDD-based Approaches and Genetic Algorithms
  1997 VLSI Test Symp., Seiten: 426 - 431
• Martin Keim, M. Martin, Bernd Becker, Rolf Drechsler, Paul Molitor
  Polynomial Formal Verification of Multipliers
  1997 VLSI Test Symp., Seiten: 150 - 155
  » Kurzfassung anzeigen« Kurzfassung verbergen
  Kurzfassung

  Until recently, verifying multipliers with formal methods was not feasible, even for small input word sizes. About two years ago, a new data structure, called Multiplicative Binary Moment Diagram (*BMD), was introduced for representing arithmetic functions over Boolean variables. Based on this data structure, methods were proposed by which verification of multipliers with input word sizes of up to 256 bits became now feasible. Only experimental data has been provided for these verification methods until now. In this paper we give a formal proof that logic verification using *BMDs is polynomially bounded in both space and time, when applied to the class of Wallace-tree like multipliers.

1995

 nach oben zur Jahresübersicht

• R. Krieger, Bernd Becker, Martin Keim
  Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy
  1995 IEEE Design Automation Conference, Seiten: 339 - 344
  » Kurzfassung anzeigen« Kurzfassung verbergen
  Kurzfassung

  Fault simulation for synchronous sequential circuits is a very time-consuming task. The complexity of the task increases if there is no information about the initial state of the circuit. In this case an unknown initial state is assumed which is usually handled by introducing a three-valued logic. As it is well-known fault simulation based on this logic only determines a lower bound of the fault coverage. Recently it was shown that fault simulation based upon the multiple observation time test strategy can improve the accuracy of the fault coverage. In this paper we describe how this strategy can be successfully implemented based on Ordered Binary Decision Diagrams. Our experiments demonstrate the efficiency of the fault simulation procedure developed.