Test and Reliability - Sommersemester 2022

The manufacturing process of integrated circuits (ICs, chips) is a yield process, i.e. some of the ICs will be inherently prone to failures. Since shipping of defective chips implies high follow-up costs, a test phase is necessary to detect defective chips as early as possible. Today, the so-called structural test flow is widely accepted. Here, defects are abstracted with the help of fault models and test patterns are generated that guarantee a high fault coverage with respect to the fault model considered. Taken together, test costs are responsible for up to 40% of the IC’s production costs. Furthermore, it is widely accepted that already during the design phase testability has to be taken into account (design for testability, DFT). Because of this, at least a basic knowledge of IC test issues is of importance also for IC designers.

Consequently, the course starts with standard test topics like fault models, (stuck-at)-fault simulation and automatic test pattern generation (ATPG). We will also provide an introduction to DFT methods, in particular scan design and built-in self-test. Finally, current research topics such as defect based testing, non-standard fault models, test for systems-on-a-chip (SOCs), variation aware testing, robustness analysis are addressed.