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Design and Verification of Digital Systems with VHDL - Wintersemester 03/04


Beschreibung Inhalt der Vorlesung:
The design of digital systems usually takes place on a higher level of abstraction than the transistor- or gate-level. In practice, hardware description languages like VHDL and Verilog are used to design such systems. They allow to design circuits on several layers of abstraction (gate-level, register-transfer-level, behavioral description).

This course will address the language VHDL. First, a short overview of the design process will be given. Then, VHDL will be described. The focus is on synthesis. Differences of the synthesis- and the simulation-semantics will be emphasized, which frequently lead to problems in industry.

Especially during formal verification, problems caused by synthesis-simulation-mismatches occur.

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