Security Aspects of Embedded Systems - Sommersemester 09

Literatur

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EinfÃ¼hrende Literatur (von allen Seminarteilnehmern zu lesen)

C.E. Irvine and K. Levitt. Trusted Hardware: Can It Be Trustworthy? Design Automation Conf. 2007.
Link: Irvine and Levitt

A. Perrig, J. Stankovic, and D. Wagner. Security in Wireless Sensor Networks. Communications of the ACM 2004.
Link: Perrig et al.

Themenbereich I: Angriffsszenarien

Thema 1: P. Kocher et al., Security as a New Dimension in Embedded System Design. Design Automation Conf. 2004.
Link: Kocher et al.

Thema 2: M. Bond and R. Andersson. API-Level Attacks on Embedded Systems. IEEE Computer 2001.
Link: Ross and Andersson

Thema 3: Z. Wang and R.B. Lee. Covert and Side Channels Due to Processor Architecture. Annual Comp. Security Applications Conf. 2006.
Link: Wang and Lee

Thema 4: O. KÃ¶mmerling and M.G. Kuhn. Design Principles for Tamper-Resistant Smartcard Processors. Working paper, 1999.
Link: KÃ¶mmerling and Kuhn
Auf Wunsch kann auch diese Folgearbeit bearbeitet werden:
R. Anderson and M. Kuhn. Low Cost Attacks on Tamper Resistant Devices. Book chapter in Security Protocols, 1998.
Link: Anderson and Kuhn.

Themenbereich II: Modellierung

Thema 5: B. Schneier and A. Shostack. Breaking Up Is Hard To Do: Modeling Security Threats for Smart Cards. Working paper, 1999.
Link: Schneier and Shostack

Thema 6: F. Menichelli et al., High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips, IEEE Trans. on Dependable and Secure Comp. 2008.
Link: Menichelli et al.

Themenbereich III: Schutzstrategien

Thema 7: H.V. Ramasamy et al. A Parsimonious Approach for Obtaining Resource-Efficient and Trustworthy Execution. IEEE Trans. on Dependable and Secure Comp. 2007.
Link: Ramasamy et al.

Thema 8: N. Nakka et al. An Architectural Framework for Providing Reliability and Security Support. International Conf. Dependable Systems and Networks 2004.
Link: Nakka et al.
Auf Wunsch kann auch diese Folgearbeit bearbeitet werden:
P. Dabrowski et al. Hardware Implementation of Information Flow Signatures Derived via Program Analysis. Workshop on Dependable and Secure Nanocomputing 2008.
Link: Dabrowski et al.