2010

 back to the year overview

• Alexander Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
  Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis
  2010 International Journal of Parallel Programming, volume: 38, issue: 3-4, pages: 185 - 202
  » show abstract« hide abstract
  Abstract

  Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.

2009

 back to the year overview

• Alexander Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
  Dynamic Compaction in SAT-Based ATPG
  2009 IEEE Asian Test Symp.
• Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian
  SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges
  2009 ACM Trans. on Design Automation of Electronic Systems, volume: 14, issue: 4, pages: 56:1 - 56:21
• Nicolas Houarche, Alejandro Czutro, Mariane Comte, Piet Engelke, Ilia Polian, Bernd Becker, Michel Renovell
  An Electrical Model for the Fault Simulation of Small-Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects
  2009 VLSI Test Symp.
• Nicolas Houarche, Alejandro Czutro, Mariane Comte, Piet Engelke, Ilia Polian, Bernd Becker, Michel Renovell
  Deriving an Electrical Model for Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects
  2009 Latin-American Test Workshop
• Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
  TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis
  2009 Int'l Conf. on VLSI Design, pages: 227 - 232

2008

 back to the year overview

• Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker
  A Simulator of Small-Delay Faults Caused by Resistive-Open Defects
  2008 IEEE European Test Symp., pages: 113 - 118
• Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
  TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis
  2008 edaWorkshop
• Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker
  On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
  2008 IEEE Trans. on CAD, volume: 27, issue: 2, pages: 327 - 338
  » show abstract« hide abstract
  Abstract

  Test application at reduced power supply voltage (low-voltage testing) or reduced temperature (low-temperature testing) can improve the defect coverage of a test set, in particular of resistive short defects. Using a probabilistic model of these defects, we quantify the coverage impact of low-voltage and low-temperature testing for different voltages and temperatures. When considering the coverage increase, we differentiate between defects missed by the test set at nominal conditions and undetectable defects (flaws) detected at non-nominal conditions. In our analysis, the performance degradation of the device caused by lower power supply voltage is accounted for. Furthermore, we describe a situation in which defects detected by conventional testing are missed by low-voltage testing and quantify the resulting coverage loss. Experimental results suggest that test quality is improved even if no cost increase is allowed. If multiple test applications are acceptable, a combination of low-voltage and low-temperature turns out to provide the best coverage of both hard defects and flaws.
• Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
  Automatic Test Pattern Generation for Interconnect Open Defects
  2008 VLSI Test Symp., pages: 181 - 186
• Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
  Automatic Test Pattern Generation for Interconnect Open Defects
  2008 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
• Ilia Polian, Yusuke Nakamura, Piet Engelke, Stefan Hillebrecht, Kohei Miyase, Seiji Kajihara, Bernd Becker, Xiaoqing Wen
  Diagnose realistischer Defekte mit Hilfe des X-Fehlermodells
  2008 GMM/GI/ITG Reliability and Design Conf., pages: 155 - 156
• Ilia Polian, Yusuke Nakamura, Piet Engelke, Stefan Spinner, Kohei Miyase, Seiji Kajihara, Bernd Becker, Xiaoqing Wen
  Diagnosis of Realistic Defects Based on the X-Fault Model
  2008 IEEE Design and Diagnostics of Electronic Circuits and Systems, pages: 263 - 268
• Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
  Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model
  2008 Int'l Test Conf., pages: 1 - 10
• Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker
  Resistive Bridging Fault Simulation of Industrial Circuits
  2008 Conf. on Design, Automation and Test in Europe, pages: 628 - 633
  » show abstract« hide abstract
  Abstract

  We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophisticated RBF model, the run times of the simulator were within an order of magnitude of the run times for pattern-parallel complete-circuit stuck-at fault simulation. Industrial-size circuits, including a multi-million-gates design, could be simulated in reasonable time despite a significantly higher number of faults to be simulated compared with stuck-at fault simulation.
• Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker
  Resistive Bridging Fault Simulation of Industrial Circuits
  2008 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”

2007

 back to the year overview

• Piet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker
  SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges
  2007 IEEE Asian Test Symp., pages: 433 - 438
  » show abstract« hide abstract
  Abstract

  A high-performance resistive bridging fault simulator SUPERB (Simulator Utilizing Parallel Evaluation of Resistive Bridges) is proposed. It is based on fault sectioning in combination with parallel-pattern or parallel-fault multiple-stuck-at simulation. It outperforms a conventional interval-based resistive bridging fault simulator by 60X to 120X while delivering identical results. Further competing tools are outperformed by several orders of magnitude.
• Stefan Spinner, Jie Jiang, Ilia Polian, Piet Engelke, Bernd Becker
  Simulating Open-Via Defects
  2007 IEEE Asian Test Symp., pages: 265 - 270
  » show abstract« hide abstract
  Abstract

  Open-via defects are a major systematic failure mechanism in nanoscale manufacturing processes. We present a flow for simulating open-via defects. Electrical parameters are extracted from the layout and technology data and represented in a way which allows efficient simulation on gate level. The simulator takes oscillation caused by open-via defects into account and quantifies its impact on defect coverage. The flow can be employed for manufacturing test as well as for defect diagnosis.

2006

 back to the year overview

• Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
  Simulating Resistive Bridging and Stuck-At Faults
  2006 IEEE Trans. on CAD, volume: 25, issue: 10, pages: 2181 - 2192
  » show abstract« hide abstract
  Abstract

  We present a simulator for resistive bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look-up, thus exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; interaction of fault effects in current time frame and earlier timeframes is elaborated on for different bridge resistances. Experimental results are given for resistive bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed and quantitative results with respect to all these definitions are given for the first time.
• Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker
  Analyzing the memory effect of resistive open in CMOS random logic
  2006 Int'l Conf. on Design and Test of Integrated Systems in Nanoscale Technology, pages: 251 - 256
  » show abstract« hide abstract
  Abstract

  This paper analyzes the electrical behaviour of resistive opens as a function of its unpredictable resistance. It is demonstrated that the electrical behaviour depends on the value of the open resistance. It is also shown that, due to the memory effect detection of the open by a given vector Ti depends on all the vectors that have been applied to the circuit before Ti. An electrical analysis of this memory effect is presented.
• Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
  Automatic Test Pattern Generation for Resistive Bridging Faults
  2006 Jour. Electronic Testing, volume: 22, issue: 1, pages: 61 - 69
  » show abstract« hide abstract
  Abstract

  An ATPG for resistive bridging faults in combinational or full-scan circuits is proposed. It combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced so far, it can handle static effects of arbitrary non-feedback bridges between two nodes, including ones detectable at higher bridge resistance and undetectable at lower resistance, and faults requiring more than one vector for detection. The developed tool is applied to ISCAS circuits, and a higher efficiency compared with other resistive bridging fault as well as stuck-at ATPG is reported. Information required for accurate resistive bridging fault simulation is obtained as a by-product.
• Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke
  X-Masking During Logic BIST and Its Impact on Defect Coverage
  2006 IEEE Trans. on VLSI Systems, volume: 14, issue: 2, pages: 193 - 202
  » show abstract« hide abstract
  Abstract

  We present a technique for making a circuit ready for Logic BIST by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.
• Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker
  A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency
  2006 IEEE Asian Test Symp., pages: 273 - 278
  » show abstract« hide abstract
  Abstract

  This paper analyzes the electrical behavior of resistive opens as a function of their unpredictable resistance. It is demonstrated that the electrical behavior depends on the value of the open resistance. It is also shown that detection of the open by a given vector Ti recursively depends on all the vectors that have been applied to the circuit before Ti. An electrical analysis of this recursive effect is presented and a specific ATPG strategy is proposed.
• Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker
  Delta-IddQ Testing of Resistive Short Defects
  2006 IEEE Asian Test Symp., pages: 63 - 68
  » show abstract« hide abstract
  Abstract

  This paper addresses the efficiency of IDDQ and more in particular Delta-IDDQ testing when using a realistic short defect model that properly considers the relation between the resistance of the short and its detectability. The results clearly show that the Delta-IDDQ approach covers a large number of resistive shorts missed by conventional logic testing, requiring only a relative small vector set. In addition a significant number of defects which are proven to be undetectable by logic testing but may deteriorate and result in reliability failures are detected. The Delta-IDDQ threshold and thus the equipment sensitivity is shown to be critical for the test quality. Furthermore, the validity of the traditional IDDQ fault models when considering resistive short defects is found to be limited. For instance, the use of the fault-free next-state function for sequential IDDQ fault simulation is shown to result in a wrong classification of some resistive short defects. This is the first systematic study of IDDQ testing of resistive short defects. The impact of the threshold on the defect coverage is quantified for the first time. Although the simulation results are based upon an older technology, the results and methodology are as well valid for state-of-the-art and NanoTechnologies.
• Piet Engelke, Ilia Polian, Hans Manhaeve, Bernd Becker
  IddQ Testing of Resistive Bridging Defects
  2006 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, pages: 123 - 124

2005

 back to the year overview

• Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
  Modeling feedback bridging faults with non-zero resistance.
  2005 Jour. Electronic Testing, volume: 21, issue: 1, pages: 57 - 69
  » show abstract« hide abstract
  Abstract

  We study the behavior of feedback bridging faults with non-zero bridge resistance in both combinational and sequential circuits. We demonstrate that a test vector may detect the fault, not detect the fault or lead to oscillation, depending on bridge resistance. Moreover, the resistance intervals in which a particular behavior is observed are not necessarily contiguous. Even loops going through a gate with controlling values on its side inputs (which we call disabled loops) expose non-trivial behavior. We outline the multiple strengths problem which arises due to the fact that a critical bridge resistance depends on the strengths of the signals driving the bridge, which in turn are functions of the number of the on-transistors, these again depending on the bridge resistance, making such a fault very hard to resolve. For sequential circuits, we describe additional difficulties caused by the need to account for implications on bridge behavior, which have originated in the previous time frames. We conclude that the complexity of resistive feedback bridging fault simulation accurate enough to resolve such situations will probably be prohibitively high and propose possible simplifying assumptions. We present simulation results for ISCAS benchmarks using these assumptions with and without taking oscillation into account.
• Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker
  An Unified Fault Model and Test Generation Procedure for Interconnect Opens and Bridges
  2005 IEEE European Test Symp., pages: 22 - 27
• Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
  Modeling feedback bridging faults with non-zero resistance
  2005 Jour. Electronic Testing, volume: 21, issue: 1, pages: 57 - 69
  » show abstract« hide abstract
  Abstract

  We study the behavior of feedback bridging faults with non-zero bridge resistance in both combinational and sequential circuits. We demonstrate that a test vector may detect the fault, not detect the fault or lead to oscillation, depending on bridge resistance. Moreover, the resistance intervals in which a particular behavior is observed are not necessarily contiguous. Even loops going through a gate with controlling values on its side inputs (which we call disabled loops) expose non-trivial behavior. We outline the multiple strengths problem which arises due to the fact that a critical bridge resistance depends on the strengths of the signals driving the bridge, which in turn are functions of the number of the on-transistors, these again depending on the bridge resistance, making such a fault very hard to resolve. For sequential circuits, we describe additional difficulties caused by the need to account for implications on bridge behavior, which have originated in the previous time frames. We conclude that the complexity of resistive feedback bridging fault simulation accurate enough to resolve such situations will probably be prohibitively high and propose possible simplifying assumptions. We present simulation results for ISCAS benchmarks using these assumptions with and without taking oscillation into account.
• Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker
  On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
  2005 IEEE Asian Test Symp., pages: 266 - 269
  » show abstract« hide abstract
  Abstract

  Resistive defects are gaining importance in very-deep-submicron technologies, but their detection conditions are not trivial. Test application can be performed under reduced temperature and/or voltage in order to improve detection of these defects. This is the first analytical study of resistive bridge defect coverage of CMOS ICs under low-temperature and mixed low-temperature, low-voltage conditions. We extend a resistive bridging fault model in order to account for temperature-induced changes in detection conditions. We account for changes in both the parameters of transistors involved in the bridge and the resistance of the short defect itself. Using a resistive bridging fault simulator, we determine fault coverage for low-temperature testing and compare it to the numbers obtained at nominal conditions. We also quantify the coverage of flaws,i.e. defects that are redundant at nominal conditions but could deteriorate and become early-life failures. Finally, we compare our results to the case of low-voltage testing and comment on combination of these two techniques.
• Ilia Polian, Sandip Kundu, Jean-Marc Galliere, Piet Engelke, Michel Renovell, Bernd Becker
  Resistive Bridge Fault Model Evolution From Conventional to Ultra Deep Submicron Technologies
  2005 VLSI Test Symp., pages: 343 - 348
  » show abstract« hide abstract
  Abstract

  We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) and a technology-specific part. The first model is based on Shockley equations and is valid for conventional but not deep submicron CMOS. The second model is obtained by fitting SPICE data. The third resistive bridging fault model uses Berkeley Predictive Technology Model and BSIM4; it is valid for CMOS technologies with feature sizes of 90nm and below, accurately describing non-trivial electrical behavior in that technologies. Experimental results for ISCAS circuits show that the test patterns obtained for the Shockley model are still valid for the Fitted model, but lead to coverage loss under the Predictive model.
• Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
  Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
  2005 IEEE Design and Diagnostics of Electronic Circuits and Systems, pages: 43 - 48
• Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
  Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
  2005 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, pages: 16 - 20
• Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
  Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
  2005 IEEE Int'l Workshop on Current and Defect-Based Testing, pages: 43 - 48

2004

 back to the year overview

• Yuyi Tang, Hans-Joachim Wunderlich, Harald Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
  X-masking during logic BIST and its impact on defect coverage
  2004 IEEE Int'l Workshop on Test Resource Partitioning, pages: 442 - 451
• Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
  Automatic test pattern generation for resistive bridging faults
  2004 IEEE European Test Symp., pages: 160 - 165
• Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
  Automatic test pattern generation for resistive bridging faults
  2004 IEEE Int'l Workshop on Current and Defect-Based Testing, pages: 89 - 94
• Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
  The Pros and Cons of Very-Low-Voltage Testing: An Analysis Based on Resistive Short Defects
  2004 VLSI Test Symp., pages: 171 - 178
• Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
  The Pros and Cons of Very-Low-Voltage Testing: An Analytical View
  2004 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, pages: 149 - 153
• Yuyi Tang, Hans-Joachim Wunderlich, Harald Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
  X-masking during logic BIST and its impact on defect coverage
  2004 Int'l Test Conf., pages: 442 - 451
  » show abstract« hide abstract
  Abstract

  We present a technique for making a circuit ready for Logic BIST by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.

2003

 back to the year overview

• Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
  Modelling Feedback Bridging Faults With Non-Zero Resistance
  2003 European Test Workshop, pages: 91 - 96
  » show abstract« hide abstract
  Abstract

  We study the behavior of feedback bridging faults with non-zero bridge resistance in both combinational and sequential circuits. We demonstrate that a test vector may detect the fault, not detect the fault or lead to oscillation, depending on bridge resistance. Moreover, the resistance intervals in which a particular behavior is observed are not necessarily contiguous. Even loops going through a gate with controlling values on its side inputs (which we call disabled loops) expose non-trivial behavior. We outline the multiple strengths problem which arises due to the fact that a critical bridge resistance depends on the strengths of the signals driving the bridge, which in turn are functions of the number of the on-transistors, these again depending on the bridge resistance, making such a fault very hard to resolve. For sequential circuits, we describe additional difficulties caused by the need to account for implications on bridge behavior, which have originated in the previous time frames. We conclude that the complexity of resistive feedback bridging fault simulation accurate enough to resolve such situations will probably be prohibitively high and propose possible simplifying assumptions. We present simulation results for ISCAS benchmarks using these assumptions with and without taking oscillation into account.
• Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
  Simulating Resistive Bridging Faults
  2003 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, pages: 92 - 97
  » show abstract« hide abstract
  Abstract

  We present a simulator for resistive bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look-up, thus exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; reciprocal action of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed and quantitative results with respect to all these definitions are given for the first time.
• Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
  Simulating Resistive Bridging and Stuck-At Faults
  2003 Int'l Test Conf., pages: 1051 - 1059
• Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
  Simulating Resistive Bridging and Stuck-at Faults
  2003 IEEE Int'l Workshop on Current and Defect-Based Testing, pages: 49 - 56
  » show abstract« hide abstract
  Abstract

  We present a simulator for resistive bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look-up, thus exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; reciprocal action of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed and quantitative results with respect to all these definitions are given for the first time.

2002

 back to the year overview

• Ilia Polian, Piet Engelke, Bernd Becker
  Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics
  2002 Int'l Symp. on Multi-Valued Logic, pages: 216 - 222
  » show abstract« hide abstract
  Abstract

  We present the concept of a multi-valued logic simulator for bridging faults in sequential circuits. Different models for the handling of intermediate values in flip-flops on the digital design level can be integrated and result in an Expected realistic behavior area for bridging faults. Several experimental results are given to underline properties and advantages of the simulation technique

2000

 back to the year overview

• Piet Engelke, Bernd Becker, Martin Keim
  A Parameterizable Fault Simulator for Bridging Faults
  2000 European Test Workshop, pages: 63 - 68
• Martin Keim, Piet Engelke, Bernd Becker
  A Parameterizable Fault Simulator for Bridging Faults
  2000 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”