Rechnerarchitektur - Universität Freiburg

Name	John P. Hayes, Prof.
Adresse	Department of Electrical Engineering and Computer Science EECS Bldg. Room 2114E University of Michigan 1301 Beal Avenue Ann Arbor, MI 48109-2122, USA.
Telefon	+1 (734) 763-0386
Fax	+1 (734) 763-4617
eMail	jhayes@eecs.umich.edu
Website	http://www.eecs.umich.edu/~jhayes/
Biographie	Since 1982, John P. Hayes has been a professor in the EECS Department at the University of Michigan, where he holds the Claude E. Shannon Chair of Engineering Science. Prior to that he was on the faculty of the University of Southern California. He also worked in industry for several years, and has held visiting positions at Stanford University, McGill University, and the Universite de Montreal. Professor Hayes teaches and conducts research in the general area of computer science and engineering, with specific interests in computer hardware design, quantum computing, computer-aided design, testing, and verification of digital systems, VLSI design, and fault-tolerant and embedded computer systems. He was the founding director of Michigan's Advanced Computer Architecture Laboratory. He is the author of several books including Computer Architecture and Organization, (McGraw-Hill, 3rd ed. 1998), Layout Minimization for CMOS Cells, (Kluwer, 1992), and Introduction to Digital Logic Design, (Addison-Wesley, 1993), as well as numerous technical papers. He received the B.E. degree from the National University of Ireland, Dublin and his M.S. and Ph.D. degrees from the University of Illinois, Urbana-Champaign. He received the University of Michigan’s Distinguished Faculty Award in 1999 and the Humboldt Research Award in 2004. Professor Hayes is a Fellow of both IEEE and ACM.
Kommentar	Prof. Hayes ist Preisträger der Alexander von Humboldt Stiftung. Im Zuge dessen ist Prof. Hayes vom 01.02.2004 bis 15.08.2004 am Institut für Informatik, und wird sich innerhalb der Arbeitsgruppe Rechnerarchitektur der Forschung zum Thema "Test und Verifikation von Digitalschaltungen im Zeitalter der Nanotechnologie" widmen.

John P. Hayes

Jahre: 2007 | 2006 | 2005 | 2004

2007

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John P. Hayes, Ilia Polian, Bernd Becker
An Analysis Framework for Transient-Error Tolerance
2007 VLSI Test Symp., Seiten: 249 - 255
Ilia Polian, John P. Hayes, Bernd Becker
Cost-Efficient Circuit Hardening Based on Critical Soft Error Rate
2007 IEEE Workshop on RTL ATPG and DfT
Ilia Polian, John P. Hayes, Damian Nowroth, Bernd Becker
Ein kostenbegrenzter Ansatz zur Reduktion der transienten Fehlerrate
2007 GMM/GI/ITG Reliability and Design Conf., Seiten: 183 - 184

2006

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John P. Hayes, Ilia Polian, Bernd Becker
A Model for Transient Faults in Logic Circuits
2006 Int'l Design and Test Workshop

2005

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John P. Hayes, Ilia Polian, Thomas Fiehn, Bernd Becker
A Family of Logical Fault Models for Reversible Circuits
2005 IEEE European Test Symp., Seiten: 65 - 70
KurzfassungReversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional circuits such as stuck-at models are not well-suited to quantum circuits. We derive a family of logical fault models for reversible circuits composed of k-CNOT (k-input controlled-NOT) gates and implementable by many technologies. The models are extensions of the previously proposed single missing-gate fault (MGF) model, and include multiple and partial MGFs. We study the basic detection requirements of the new fault types and derive bounds on the size of their test sets. We also present optimal test sets computed via integer linear programming for various benchmark circuits. These results indicate that, although the test sets are generally very small, partial MGFs may need significantly larger test sets than single MGFs.
Ilia Polian, John P. Hayes, Thomas Fiehn, Bernd Becker
A Family of Logical Fault Models for Reversible Circuits
2005 IEEE Asian Test Symp., Seiten: 422 - 427
KurzfassungReversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional circuits such as stuck-at models are not well-suited to quantum circuits. We derive a family of logical fault models for reversible circuits composed of k-CNOT (k-input controlled-NOT) gates and implementable by many technologies. The models are extensions of the previously proposed single missing-gate fault (MGF) model, and include multiple and partial MGFs. We study the basic detection requirements of the new fault types and derive bounds on the size of their test sets. We also present optimal test sets computed via integer linear programming for various benchmark circuits. These results indicate that, although the test sets are generally very small, partial MGFs may need significantly larger test sets than single MGFs.
Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker
Transient Fault Characterization in Dynamic Noisy Environments
2005 Int'l Test Conf., Seiten: 10 pp. - 1048

2004

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John P. Hayes, Ilia Polian, Bernd Becker
Testing for Missing-Gate Faults in Reversible Circuits
2004 IEEE Asian Test Symp., Seiten: 100 - 105
KurzfassungLogical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of reversible elements called k-CNOT (controllable NOT) gates. We review the characteristics of k-CNOT circuits and observe that traditional fault models like the stuck-at model may not accurately represent their faulty behavior or test requirements. A new fault model, the missing gate fault (MGF) model, is proposed to better represent the physical failure modes of quantum technologies. It is shown that MGFs are highly testable, and that all MGFs in an N-gate k-CNOT circuit can be detected with from one to | N / 2 | test vectors. A design-for-test (DFT) method to make an arbitrary circuit fully testable for MGFs using a single test vector is described. Finally, we present simulation results to determine (near) optimal test sets and DFT configurations for some benchmark circuits.