2017

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• Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker
  TSO Tests
  2017 IEEE VLSI Test Symposium (VTS'17)
• Jan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker
  Fast and Waveform-Accurate Hazard-Aware SAT-Based TSOF ATPG
  2017 Conference on Design, Automation and Test in Europe
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  Kurzfassung

  unaware tests will fail to detect the targeted opens because of test invalidation – these are reliably detected by our new test generation methodology. Importantly, our approach can also be applied to improve the effectiveness of commercial cell aware tests.

2015

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• Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
  Multi-Cycle Circuit Parameter Independent ATPG for Interconnect Open Defects
  2015 33rd VLSI Test Symposium (VTS)
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  Kurzfassung

  In this work we extend the validity of CPI tests by introducing so-called multi-cycle CPI tests and single-value CPI tests. By doing so, we significantly improve the coverage of open defects and ensure their detection whilst including the additional effect of leakage currents on opens. Experimental results for circuits with over 500k non-equivalent faults and several thousand aggressors %deriving the new classes of CPI tests show the effectiveness of the newly proposed CPI tests as well as the high efficiency of a new ATPG algorithm to generate these new classes of CPI tests.

2014

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• Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
  for Interconnect Open Defects
  2014 23nd IEEE Asian Test Symposium (ATS)
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  Kurzfassung

  faults and several thousand aggressors.
• Matthias Sauer, Sven Reimer, Sudhakar M. Reddy, Bernd Becker
  Efficient SAT-based Circuit Initialization for Large Designs
  2014 Int'l Conf. on VLSI Design
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  Kurzfassung

  We present a procedure to determine initialization sequences for a sequential circuit optimizing sequence length and unknown values (Xes) in the flip-flops. Specifically, we consider the following two problems: (1) Determine a sequence that initializes a maximal set of flip-flops starting in a completely unknown state. (2) Determine a minimal subset of flip-flops that need to be controllable such that the circuit can be completely initialized in a limited number of time frames. The underlying principle of our methods is a maximization formalism using formal optimization techniques based on satisfiability solvers (MaxSAT). We introduce several heuristics which increase the scalability of our approach significantly. Experimental results demonstrate the applicability of the method for large academic and industrial benchmark circuits with up to a few hundred thousand gates.

2012

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• Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Sudhakar M. Reddy, Bernd Becker
  Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation
  2012 Int'l Conf. on VLSI Design
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  Kurzfassung

  Test pattern generation for sequential circuits benefits from scanning strategies as these allow the justification of arbitrary circuit states. However, some of these states may be unreachable during normal operation. This results in non-functional operation which may lead to abnormal circuit behaviour and result in over-testing. In this work, we present a versatile approach that combines a highly adaptable SAT-based path-enumeration algorithm with a model-checking solver for invariant properties that relies on the theory of Craig interpolants to prove the unreachability of circuit states. The method enumerates a set of longest sensitisable paths and yields test sequences of minimal length able to sensitise the found paths starting from a given circuit state. We present detailed experimental results on the reach ability of sensitisable paths in ITC 99 circuits.
• Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
  Functional Justification in Sequential Circuits using SAT and Craig Interpolation
  2012 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
• Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
  Functional Test of Small-Delay Faults using SAT and Craig Interpolation
  2012 Int'l Test Conf., Seiten: 1 - 8
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  Kurzfassung

  We present SATSEQ, a timing-aware ATPG system for small-delay faults in non-scan circuits. The tool identifies the longest paths suitable for functional fault propagation and generates the shortest possible sub-sequences per fault. Based on advanced model-checking techniques, SATSEQ provides detection of small-delay faults through the longest functional paths. All test sequences start at the circuit's initial state; therefore, overtesting is avoided. Moreover, potential invalidation of the fault detection is taken into account. Experimental results show high detection and better performance than scan testing in terms of test application time and overtesting-avoidance.

2010

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• Alexander Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
  Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis
  2010 International Journal of Parallel Programming, Band: 38, Nummer: 3-4, Seiten: 185 - 202
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  Kurzfassung

  Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.

2009

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• Alexander Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
  Dynamic Compaction in SAT-Based ATPG
  2009 IEEE Asian Test Symp.
• Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
  TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis
  2009 Int'l Conf. on VLSI Design, Seiten: 227 - 232

2008

 nach oben zur Jahresübersicht

• Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
  TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis
  2008 edaWorkshop
• Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, X. Tang, Bernd Becker
  No Free Lunch in Error Protection?
  2008 Workshop on Dependable and Secure Nanocomputing
• Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, X. Tang, Bernd Becker
  On Reducing Circuit Malfunctions Caused by Soft Errors
  2008 Int'l Symp. on Defect and Fault Tolerance, Seiten: 245 - 253
• Ilia Polian, Sudhakar M. Reddy, Bernd Becker
  Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors
  2008 IEEE Int'l Symp. on VLSI, Seiten: 257 - 262

2005

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• Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker
  An Unified Fault Model and Test Generation Procedure for Interconnect Opens and Bridges
  2005 IEEE European Test Symp., Seiten: 22 - 27

2004

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• Ilia Polian, Irith Pomeranz, Sudhakar M. Reddy, Bernd Becker
  On the use of maximally dominating faults in n-detection test generation
  2004 IEE Proceedings Computers and Digital Techniques, Band: 151, Nummer: 3, Seiten: 235 - 244
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  Kurzfassung

  The size of an n-detection test set increases approximately linearly with n. This increase in size may be too fast when an upper bound on test set size must be satisfied. We propose a test generation method for obtaining a more gradual increase in the sizes of n-detection test sets, while still ensuring that every additional test would be useful in improving the test set quality. The method is based on the use of fault dominance relations to identify a small subset of faults (called maximally dominating faults) whose numbers of detections are likely to have a high impact on the defect coverage of the test set. We use structural analysis to obtain a superset of the maximally dominating fault set. We also propose a method for determining exact sets of maximally dominating faults. We define new types of n-detection test sets based on the approximate and exact sets of maximally dominating faults. The test sets are called (n,n2)-detection test sets and (n,n2,n3)-detection test sets. We present experimental results to demonstrate the usefulness of these test sets in producing high-quality n-detection test sets for the combinational logic of ISCAS-89 benchmark circuits.

2003

 nach oben zur Jahresübersicht

• Ilia Polian, Bernd Becker, Sudhakar M. Reddy
  Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST
  2003 Conf. on Design, Automation and Test in Europe, Seiten: 1184 - 1185

1996

 nach oben zur Jahresübersicht

• Harry Hengster, U. Sparmann, Bernd Becker, Sudhakar M. Reddy
  Local Transformations and Robust Dependent Path Delay Faults
  1996 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
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  Kurzfassung

  Local transformations are used in several synthesis approaches. During application of such transformations attention has to be paid to many important properties, e.g. area, speed, power consumption, and testability. In this paper we study relations between local transformations and delay fault testability. In delay testing it is not necessary to test every path in a circuit to ascertain correct timing behavior. For example, a set of robust dependent path delay faults need not to be considered for testing if all paths that are not robust dependent are tested. We will present sufficient conditions for local transformations which ensure that a test set for all non-robust-dependent paths in the original circuit is also a test set for all non-robust-dependent paths in the transformed circuit. These conditions are applied to some local transformations which are often used in logic synthesis and it is shown that they preserve testability. The impact of local transformations on robust dependent testability is demonstrated by experimental results performed on benchmark circuits.
• Harry Hengster, U. Sparmann, Bernd Becker, Sudhakar M. Reddy
  Local Transformations and Robust Dependent Path Delay Faults
  1996 European Test Workshop
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  Kurzfassung

  Local transformations are used in several synthesis approaches. During application of such transformations attention has to be paid to many important properties, e.g. area, speed, power consumption, and testability. In this paper we study relations between local transformations and delay fault testability. In delay testing it is not necessary to test every path in a circuit to ascertain correct timing behavior. For example, a set of robust dependent path delay faults need not to be considered for testing if all paths that are not robust dependent are tested. We present sufficient conditions for local transformations which ensure that a test set for all non-robust-dependent paths in the original circuit is also a test set for all non-robust-dependent paths in the transformed circuit. These conditions are applied to some local transformations which are often used in logic synthesis and it is shown that they preserve testability. The impact of local transformations on robust dependent testability is demonstrated by experimental results performed on benchmark circuits.
• Harry Hengster, U. Sparmann, Bernd Becker, Sudhakar M. Reddy
  Local Transformations and Robust Dependent Path Delay Faults
  1996 Int'l Test Conf.
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  Kurzfassung

  Local transformations are used in several synthesis approaches. During application of such transformations attention has to be paid to many important properties, e.g. area, speed, power consumption, and testability. In this paper we study relations between local transformations and delay fault testability. In delay testing it is not necessary to test every path in a circuit to ascertain correct timing behavior. For example, a set of robust dependent path delay faults need not be considered for testing if all paths that are not robust dependent are tested. We present sufficient conditions for local transformations which ensure that a test set for all non-robust-dependent paths in the original circuit is also a test set for all non-robust-dependent paths in the transformed circuit. These conditions are applied to some local transformations which are often used in logic synthesis and it is shown that they preserve testability. The impact of local transformations on robust dependent testability is demonstrated by experimental results performed on benchmark circuits.