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Name Rolf Drechsler, Prof. Dr. Rolf Drechsler, Prof. Dr.
Adresse Arbeitsgruppe Rechnerarchitektur
Universität Bremen FB3
Bibliothekstrasse 1 - [MZH]
28359 Bremen
Telefon +49 [421] 218 - 7389
Fax +49 [421] 2 18 - 73 85
eMail drechsle@informatik.uni-bremen.de
Website http://www.informatik.uni-bremen.de/grp/ag-ram/

Rolf Drechsler

Jahre: 2014 | 2004 | 2003 | 2002 | 2001 | 2000 | 1999 | 1998 | 1997 | 1996 | 1995 | 1994 | 1993 | 1992

    2014

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    2004

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    • Thomas Eschbach, Rolf Drechsler, Bernd Becker
      Placement and Routing Optimization for Circuits Derived from BDDs
      2004 IEEE Int'l Symp. on Circuits and Systems, Seiten: V229 - V232

    2003

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    • Frank Schmiedle, Rolf Drechsler, Bernd Becker
      Exact Routing with Search Space Reduction
      2003 IEEE Trans. on Computers, Band: 52, Nummer: 6, Seiten: 815 - 825
    • Martin Keim, M. Martin, Bernd Becker, Rolf Drechsler, Paul Molitor
      Polynomial Formal Verification of Multipliers
      2003 Formal Methods in System Design, Band: 22, Nummer: 1, Seiten: 39 - 58
    • Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, L. Linhard, G. Angst
      Recursive Bi-Partitioning of Netlists for Large Number of Partitions
      2003 Journal of Systems Architecture, Band: 49, Nummer: 12-15, Seiten: 521 - 528

    2002

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    • Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker
      Crossing Reduction by Windows Optimization
      2002 Int'l Symp. on Graph Drawing, Band: 2528, Seiten: 285 - 294
    • Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, L. Linhard, G. Angst
      Recursive Bi-Partitioning of Netlists for Large Number of Partitions
      2002 Euromicro Conf., Seiten: 38 - 44
    • Klaus-Jürgen Englert, Rolf Drechsler, Bernd Becker
      Verification of HDLs using Symbolic Set Representation
      2002 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”

    2001

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    • Rolf Drechsler, J. Römmler
      Implementation and Visualization of a BDD Package in JAVA
      , 2001
    • Rolf Drechsler
      Educational Software for Computer Engineering: A Case Study of an Interactive BDD Tool
      2001 IEEE Computer Society Learning Technology Task Force, Band: 3, Nummer: 3
    • Bernd Becker, Rolf Drechsler, Thomas Eschbach, Wolfgang Günther
      GREEDY IIP: Partitioning Large Graphs by Greedy Iterative Improvement
      2001 Euromicro Conf., Seiten: 54 - 60
    • Nicole Drechsler, Frank Schmiedle, Daniel Große, Rolf Drechsler
      Heuristic Learning based on Genetic Programming
      2001 EuroGP, Springer Verlag, Band: 2038, Seiten: 1 - 10
    • Wolfgang Günther, Rolf Drechsler
      Implementation of Read-k-times BDDs on top of standard BDD packages
      2001 Int'l Conf. on VLSI Design, Seiten: 173 - 178
    • Rolf Drechsler, Wolfgang Günther, L. Linhard, G. Angst
      Level Assignment for Displaying Combinational Logic
      2001 Euromicro Conf., Seite: 148
    • Wolfgang Günther, Rolf Drechsler
      Performance Driven Optimization for MUX based FPGAs
      2001 Int'l Conf. on VLSI Design, Seiten: 311 - 316
    • Frank Schmiedle, Nicole Drechsler, Daniel Große, Rolf Drechsler
      Priorities in Multi-Objective Optimization for Genetic Programming
      2001 Conf. on Genetic and Evolutionary Computation, Seiten: 129 - 136
    • Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
      Selection of Efficient Re-Ordering Heuristics for MDD Construction
      2001 Int'l Symp. on Multi-Valued Logic, Seiten: 299 - 304
    • M. Thornton, Rolf Drechsler, D. M. Miller
      Spectral Techniques in VLSI CAD
      Kluwer Academic Publisher, 2001
    • Frank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker
      Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics
      2001 Int'l Conf. on Computational Intelligence, Band: 2206, Seiten: 479 - 491
    • Rolf Drechsler, Wolfgang Günther, Fabio Somenzi
      Using Lower Bounds during Dynamic BDD Minimization
      2001 IEEE Trans. on CAD, Band: 20, Nummer: 1, Seiten: 51 - 57
    • P. Johannsen, Rolf Drechsler
      Utilizing High-Level Information for Formal Hardware Verification (Invited Talk)
      2001 Advanced Computer Systems, Seiten: 419 - 431

    2000

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    • M. A. Thornton, Rolf Drechsler, Wolfgang Günther
      A Method for Approximate Equivalence Checking
      2000 Int'l Symp. on Multi-Valued Logic, Seiten: 447 - 452
    • Wolfgang Günther, Rolf Drechsler
      ACTion: Combining Logic Synthesis and Technology Mapping for MUX based FPGAs
      2000 Journal of Systems Architecture, Band: 46, Nummer: 14, Seiten: 1321 - 1334
    • Wolfgang Günther, Rolf Drechsler
      ACTion: Combining Logic Synthesis and Technology Mapping for MUX based FPGAs
      2000 Int'l Workshop on Logic Synth.
    • Wolfgang Günther, Rolf Drechsler
      ACTion: Combining Technology Mapping and Logic Synthesis for MUX based FPGAs
      2000 Euromicro Conf., Seiten: 130 - 137
    • Rolf Drechsler, Nicole Drechsler, Elke Mackensen, Tobias Schubert, Bernd Becker
      Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System
      2000 Euromicro Conf., Seiten: 1:425 - 431
    • Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
      Dynamic Re-Encoding During MDD Minimization
      2000 Int'l Symp. on Multi-Valued Logic, Seiten: 239 - 244
    • Wolfgang Günther, Rolf Drechsler, S. Höreth
      Efficient Dynamic Minimization of Word-Level DDs based on Lower Bound Computation
      2000 Int'l Workshop on Logic Synth.
    • Wolfgang Günther, Rolf Drechsler, S. Höreth
      Efficient Dynamic Minimization of Word-Level DDs based on Lower Bound Computation
      2000 Int'l Conf. on Computer Design, Seiten: 383 - 388
    • Rolf Drechsler, Wolfgang Günther
      Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints
      2000 Conf. on Genetic and Evolutionary Computation, Seiten: 513 - 518
    • Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
      Fast Exact Minimization of BDDs
      2000 IEEE Trans. on CAD, Band: 19, Nummer: 3, Seiten: 384 - 389
    • Rolf Drechsler
      Formal Verification of Circuits
      Kluwer Academic Publishers, 2000
    • Wolfgang Günther, Rolf Drechsler
      Improving EAs for Sequencing Problems
      2000 Conf. on Genetic and Evolutionary Computation, Seiten: 175 - 180
    • Dragan Janković, Wolfgang Günther, Rolf Drechsler
      Lower Bound Sifting for MDDs
      2000 Int'l Symp. on Multi-Valued Logic, Seiten: 193 - 198
    • Wolfgang Günther, Rolf Drechsler
      On the Computational Power of Linearly Transformed BDDs
      2000 Information Processing Letters, Band: 75, Nummer: 3, Seiten: 119 - 125
    • Rolf Drechsler, Wolfgang Günther
      Optimization of Sequential Verification by History-Based Dynamic Minimization of BDDs
      2000 IEEE Int'l Symp. on Circuits and Systems, Seiten: IV:737 - IV:740
    • Tobias Schubert, Elke Mackensen, Nicole Drechsler, Rolf Drechsler, Bernd Becker
      Specialized Hardware for Implementation of Evolutionary Algorithms
      2000 Int'l Workshop on Boolean Problems, Seiten: 175 - 182
    • Tobias Schubert, Elke Mackensen, Nicole Drechsler, Rolf Drechsler, Bernd Becker
      Specialized Hardware for Implementation of Evolutionary Algorithms
      2000 Conf. on Genetic and Evolutionary Computation, Seite: 369
    • Rolf Drechsler, Wolfgang Günther, Bernd Becker
      Testability of Circuits Derived from Lattice Diagrams
      2000 Euromicro Conf., Seiten: 188 - 192
    • Rolf Drechsler, Wolfgang Günther, Bernd Becker
      Testability of Circuits Derived from Lattice Diagrams
      2000 Latin-American Test Workshop
    • Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
      Verification of Designs Containing Black Boxes
      2000 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”
    • Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
      Verification of Designs Containing Black Boxes
      2000 Euromicro Conf., Seiten: 100 - 105

    1999

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    • Rolf Drechsler, Marc Herbstritt, Bernd Becker
      Grouping Heuristics for Word-level Decision Diagrams
      1999 IEEE Int'l Symp. on Circuits and Systems, Seiten: 411 - 415
    • Rolf Drechsler, Bernd Becker
      Probabilistic IP Verification
      1999 Int'l Workshop on Testing Embedded Core-based System-Chips
    • Nicole Drechsler, Rolf Drechsler, Bernd Becker
      A New Model for Multi-Objective Optimization in Evolutionary Algorithms
      1999 Int'l Conf. on Computational Intelligence, Springer Verlag, Band: 1625, Seiten: 108 - 117
    • Christoph Scholl, D. Möller, Paul Molitor, Rolf Drechsler
      BDD Minimization Using Symmetries
      1999 IEEE Trans. on CAD, Band: 18, Nummer: 2, Seiten: 81 - 100
    • Wolfgang Günther, Rolf Drechsler
      Creating Hard Problem Instances in Logic Synthesis using Exact Minimization
      1999 IEEE Int'l Symp. on Circuits and Systems, Seiten: VI:436 - VI:439
    • Wolfgang Günther, Rolf Drechsler
      Efficient Manipulation Algorithms for Linearly Transformed BDDs
      1999 Int'l Conf. on CAD, Seiten: 50 - 53
    • Nicole Drechsler, Rolf Drechsler
      Exploiting Don't Cares During Data Sequencing using Genetic Algorithms
      1999 ASP Design Automation Conf., Seiten: 303 - 306
    • S. Höreth, Rolf Drechsler
      Formal Verification of Word-Level Specifications
      1999 Conf. on Design, Automation and Test in Europe, Seiten: 52 - 58
    • Rolf Drechsler, Marc Herbstritt, Bernd Becker
      Grouping Heuristics for Word-level Decision Diagrams
      1999 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Shaker Verlag, Seiten: 41 - 50
    • Rolf Drechsler, Wolfgang Günther
      History-based Dynamic Minimization during BDD Construction
      1999 IFIP Int'l Conf. on VLSI, Seiten: 334 - 345
    • Wolfgang Günther, Rolf Drechsler
      Minimization of BDDs using Linear Transformations based on Evolutionary Techniques
      1999 IEEE Int'l Symp. on Circuits and Systems, Seiten: I:387 - I:390
    • Wolfgang Günther, Rolf Drechsler
      Minimization of Free BDDs
      1999 ASP Design Automation Conf., Seiten: 323 - 326
    • Y. Ye, K. Roy, Rolf Drechsler
      Power Consumption in XOR-Based Circuits
      1999 ASP Design Automation Conf., Seiten: 299 - 302
    • Per Lindgren, Rolf Drechsler, Bernd Becker
      Synthesis of Pseudo Kronecker Lattice Diagrams
      1999 Int'l Conf. on Computer Design, Seiten: 307 - 310
    • Rolf Drechsler, Wolfgang Günther
      Using Lower Bounds during Dynamic BDD Minimization
      1999 IEEE Design Automation Conference, Seiten: 29 - 32
    • Rolf Drechsler, Nicole Drechsler
      VLSI CAD and the Integration of Evolutionary Techniques
      CRC Press International Series on Computational Intelligence, 1999

    1998

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    • Martin Keim, Nicole Göckel, Rolf Drechsler, Bernd Becker
      Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
      , Nummer: 105/98, 1998
    • Wolfgang Günther, Rolf Drechsler
      BDD Minimization by Linear Transformations
      1998 Advanced Computer Systems, Seiten: 525 - 532
    • Rolf Drechsler, Bernd Becker
      Binary Decision Diagrams - Theory and Implementation
      Kluwer Academic Publishers, 1998
    • Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
      Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
      1998 European Test Workshop, Seiten: 141 - 142
    • S. Höreth, Rolf Drechsler
      Dynamic Minimization of Word-Level Decision Diagrams
      1998 Conf. on Design, Automation and Test in Europe, Seiten: 612 - 617
    • G. Lee, Rolf Drechsler
      ETDD-based Generation of Complex Terms for Incompletely Specified Boolean Functions
      1998 ASP Design Automation Conf., Seiten: 75 - 80
    • Rolf Drechsler
      Evolutionary Algorithms for VLSI CAD
      Kluwer Academic Publisher, 1998
    • Rolf Drechsler, Wolfgang Günther
      Exact Circuit Synthesis
      1998 Int'l Workshop on Logic Synth., Seiten: 177 - 184
    • Rolf Drechsler, Wolfgang Günther
      Exact Circuit Synthesis
      1998 Advanced Computer Systems, Seiten: 517 - 524
    • Rolf Drechsler, Bernd Becker
      Graphenbasierte Funktionsdarstellung
      B.G. Teubner, 1998
    • M. Miller, Rolf Drechsler
      Implementing a Multiple-Valued Decision Diagram Package
      1998 Int'l Symp. on Multi-Valued Logic, Seiten: 52 - 57
    • Wolfgang Günther, Rolf Drechsler
      Linear Transformations and Exact Minimization of BDDs
      1998 Great Lakes Symp. on VLSI, Seiten: 325 - 330
    • M. Thornton, Rolf Drechsler
      Output Probability Using AND/OR Graphs
      1998 Research Report, University of Arkansas
    • M. Thornton, Rolf Drechsler
      Spectral Methods for Digital Logic Verification
      1998 Research Report, University of Arkansas
    • Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
      Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm
      1998 Int'l Symp. on Multi-Valued Logic, Seiten: 215 - 220
    • Martin Keim, Nicole Göckel, Rolf Drechsler, Bernd Becker
      Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm
      1998 Int'l Symp. on Multi-Valued Logic
    • Rolf Drechsler, Martin Sauerhoff, Detlef Sieling
      The Complexity of the Inclusion Operation on OFDDs
      1998 IEEE Trans. on CAD, Band: 17, Nummer: 5, Seiten: 457 - 459
    • Rolf Drechsler
      Verifying Integrity of Decision Diagrams
      1998 SAFECOMP, Springer Verlag, Band: 1516, Seiten: 380 - 389

    1997

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    • Rolf Drechsler, Nicole Göckel
      A Genetic Algorithm for Data Sequencing
      1997 Electronic Letters, Band: 33, Nummer: 10, Seiten: 843 - 845
    • Nicole Göckel, Martin Keim, Rolf Drechsler, Bernd Becker
      A Genetic Algorithm for Sequential Circuit Test Generation based on Symbolic Fault Simulation
      1997 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Nicole Göckel, Martin Keim, Rolf Drechsler, Bernd Becker
      A Genetic Algorithm for Sequential Circuit Test Generation based on Symbolic Fault Simulation
      1997 European Test Workshop
    • Nicole Göckel, Rolf Drechsler, Bernd Becker
      A Multi-Layer Detailed Routing Approach based on Evolutionary Algorithms
      1997 Int'l Conf. on Evolutionary Computation, Seiten: 557 - 562
    • Nicole Göckel, Rolf Drechsler
      An Evolutionary Algorithm for Minimizing BDDs of Incompletely Specified Functions
      1997 Advanced Computer Systems, Seiten: 224 - 231
    • Christoph Scholl, D. Möller, Paul Molitor, Rolf Drechsler
      BDD Minimization Using Symmetries
      , 1997
    • Rolf Drechsler, Nicole Göckel, Elke Mackensen, Bernd Becker
      BEA: Specialized Hardware for Implementation of Evolutionary Algorithms
      1997 Genetic Programming Conf., Seite: 491
    • S. Höreth, Rolf Drechsler
      Compilation of Fast Manipulation Algorithms for K*BMDs
      1997 IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Seiten: 187 - 196
    • Bernd Becker, Rolf Drechsler
      Decision Diagrams in Synthesis - Algorithms, Applications and Extensions -
      1997 Int'l Conf. on VLSI Design, Seiten: 46 - 50
    • Rolf Drechsler, A. Zuzek
      Efficient Functional Diagnosis for Synchronous Sequential Circuits Based on AND/OR Graphs
      1997 Int'l Symp. on IC Technologies, Systems and Applications, Seiten: 312 - 315
    • Rolf Drechsler
      Evolutionary Algorithms for Computer Aided Design of Integrated Circuits
      1997 Int'l Symp. on IC Technologies, Systems and Applications, Seiten: 302 - 311
    • S. Höreth, Rolf Drechsler
      Fast Construction of Kronecker Decision Diagrams from Library Based Circuits
      1997 SASIMI, Seiten: 39 - 44
    • Rolf Drechsler, Nicole Göckel, Wolfgang Günther
      Fast Exact Minimization of BDDs
      , 1997
    • Andreas Hett, Rolf Drechsler, Bernd Becker
      Fast and Efficient Construction of BDDs by reordering based Synthesis
      1997 European Design and Test Conf., Seiten: 168 - 175
    • Rolf Drechsler, Martin Keim, Bernd Becker
      Fault Simulation in Sequential Multi-Valued Logic Networks
      1997 Int'l Symp. on Multi-Valued Logic, Seiten: 145 - 150
    • Christoph Scholl, Rolf Drechsler, Bernd Becker
      Functional Simulation using Binary Decision Diagrams
      1997 GI/ITG/GME Workshop “Methoden des Entwurfs und der Verifikation digitaler Systeme”
    • Christoph Scholl, Rolf Drechsler, Bernd Becker
      Functional Simulation using Binary Decision Diagrams
      1997 Int'l Workshop on Logic Synth.
    • Rolf Drechsler, Bernd Becker
      Graphenbasierte Funktionsdarstellung
      B.G. Teubner, 1997
    • Nicole Göckel, Rolf Drechsler
      Influencing Parameters of Evolutionary Algorithms for Sequencing Problems
      1997 Int'l Conf. on Evolutionary Computation, Seiten: 575 - 580
    • Nicole Göckel, Rolf Drechsler, Bernd Becker
      Learning Heuristics for OKFDD Minimization by Evolutionary Algorithms
      1997 ASP Design Automation Conf., Seiten: 469 - 472
    • Rolf Drechsler, Nicole Göckel
      Minimization of BDDs by Evolutionary Algorithms
      1997 Int'l Workshop on Logic Synth.
    • Martin Keim, M. Martin, Bernd Becker, Rolf Drechsler, Paul Molitor
      Polynomial Formal Verification of Multipliers
      1997 VLSI Test Symp., Seiten: 150 - 155
    • Rolf Drechsler
      Pseudo Kronecker Expressions for Symmetric Functions
      1997 Int'l Conf. on VLSI Design, Seiten: 511 - 513
    • Andreas Hett, Rolf Drechsler, Bernd Becker
      Reordering Based Synthesis
      1997 iwrm
    • Rolf Drechsler
      Secure Implementation of Decision Diagrams
      1997 Int'l Workshop on Logic Synth.
    • Rolf Drechsler, R. S. Stankovic, T. Sasao
      Spectral Transforms and Word-Level Decision Diagrams
      1997 IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design
    • Rolf Drechsler, R. S. Stankovic, T. Sasao
      Spectral Transforms and Word-Level Decision Diagrams
      1997 SASIMI, Seiten: 33 - 38
    • Rolf Drechsler, Harry Hengster, H. Schäfer, J. Hartmann, Bernd Becker
      Testability of 2-Level AND/EXOR Expressions
      1997 European Design and Test Conf., Seiten: 548 - 553

    1996

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    • Rolf Drechsler, Nicole Göckel
      A Genetic Algorithm for Data Sequencing
      1996 Online Workshop on Evolutionary Computation
    • Rolf Drechsler, Bernd Becker, Nicole Göckel
      A Genetic Algorithm for the Construction of Small and Highly Testable OKFDD Circuits
      1996 Genetic Programming Conf., Seiten: 473 - 478
    • Nicole Göckel, G. Pudelko, Rolf Drechsler, Bernd Becker
      A Hybrid Genetic Algorithm for the Channel Routing Problem
      1996 IEEE Int'l Symp. on Circuits and Systems, Seiten: IV:675 - IV:678
    • Rolf Drechsler, Andreas Hett, Bernd Becker
      A Note on Symbolic Simulation using Desicion Diagrams
      1996 ulsi
    • Harry Hengster, Rolf Drechsler, S. Eckrich, T. Pfeiffer, Bernd Becker
      AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth
      1996 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Harry Hengster, Rolf Drechsler, S. Eckrich, T. Pfeiffer, Bernd Becker
      AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth
      1996 IEEE Asian Test Symp., Seiten: 148 - 154
    • Rolf Drechsler, A. Zuzek
      Efficient Functional Diagnosis for Synchronous Sequential Circuits based on AND/OR Graphs
      , 1996
    • Bernd Becker, Rolf Drechsler
      Exact Minimization of Kronecker Expressions for Symmetric Functions
      1996 IEEE Int'l Symp. on Circuits and Systems, Seiten: IV:388 - IV:391
    • Rolf Drechsler, H. Esbensen, Bernd Becker
      Genetic Algorithms in Computer Aided Design of Integrated Circuits
      1996 Online Workshop on Evolutionary Computation
    • Rolf Drechsler, Nicole Göckel, Bernd Becker
      Learning Heuristics for OBDD Minimization by Evolutionary Algorithms
      1996 Parallel Problem Solving from Nature, Springer Verlag, Band: 1141, Seiten: 730 - 739
    • Andreas Hett, Rolf Drechsler, Bernd Becker
      MORE Optimization Techniques.
      , 1996
    • Rolf Drechsler, Bernd Becker
      OKFDDs - Algorithms, Applications and Extensions
      Kluwer Academic Publisher, Seiten: 163 - 190, 1996
    • Bernd Becker, Rolf Drechsler, Reinhard Enders
      On the Computational Power of Bit-Level and Word-Level Decision Diagrams
      1996 GI/ITG/GME Workshop “Methoden des Entwurfs und der Verifikation digitaler Systeme”
    • Rolf Drechsler
      Pseudo Kronecker Expressions for Symmetric Functions
      , 1996
    • Rolf Drechsler, Harry Hengster, H. Schäfer, Bernd Becker
      Testability of AND/EXOR Expressions
      1996 European Test Workshop
    • Andreas Hett, Rolf Drechsler, Bernd Becker
      The DD Package PUMA - An Online Documentation
      https://ira.informatik.uni-freiburg.de/software/puma/, 1996
    • Rolf Drechsler
      Verification of Multi-Valued Logic Networks
      1996 Int'l Symp. on Multi-Valued Logic, Seiten: 10 - 15

    1995

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    • Rolf Drechsler, Bernd Becker, Nicole Göckel
      A Genetic Algorithm for 2-Level AND/EXOR Minimization
      1995 SASIMI, Seiten: 49 - 56
    • Rolf Drechsler, Bernd Becker, Nicole Göckel
      A Genetic Algorithm for Variable Ordering of OBDDs
      1995 Int'l Workshop on Logic Synth., Seiten: 5c:5.55 - 5.64
    • Rolf Drechsler, Bernd Becker, Nicole Göckel
      A Genetic Algorithm for Variable Ordering of OBDDs
      , Nummer: 5/95, 1995
    • Harry Hengster, Rolf Drechsler, Bernd Becker
      AND/OR/EXOR based Synthesis of KFDD-Circuits with Small Depth
      1995 Reed-Muller Colloquium UK
    • Rolf Drechsler, Bernd Becker, S. Ruppertz
      Dynamic Minimization of K*BMDs
      , 1995
    • Rolf Drechsler, Bernd Becker
      Dynamic Minimization of OKFDDs
      , Nummer: 5/95, 1995
    • Bernd Becker, Rolf Drechsler
      Exact Minimization of Kronecker Expressions for Symmetric Functions
      1995 IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Seiten: 240 - 245
    • Bernd Becker, Rolf Drechsler, M. Theobald
      OKFDDs versus OBDDs and OFDDs
      1995 ICALP, Springer Verlag, Band: 944, Seiten: 475 - 486
    • Bernd Becker, Rolf Drechsler, Reinhard Enders
      On the Computational Power of Bit-Level and Word-Level Decision Diagrams
      , 1995
    • Bernd Becker, Rolf Drechsler, R. Werchner
      On the Relation Between BDDs and FDDs
      1995 Information and Computation, Band: 123(2), Seiten: 185 - 197
    • Rolf Drechsler
      Ordered Kronecker Functional Decision Diagrams und ihre Anwendungen
      Modell Verlag, Ph.D. thesis at J.W. Goethe-Universität, 1995
    • Rolf Drechsler, Bernd Becker
      PUMA: An OKFDD-Package and its Implementation
      1995 European Design and Test Conf.
    • Bernd Becker, Rolf Drechsler
      Synthesis for Testability: Circuits Derived from Ordered Kronecker Functional Decision Diagrams
      1995 European Design and Test Conf., Seite: 592

    1994

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    • Rolf Drechsler
      BiTeS: A BDD based test pattern generator for strong robust path delay faults
      1994 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Rolf Drechsler
      BiTeS: A BDD based test pattern generator for strong robust path delay faults
      1994 European Design Automation Conf., Seiten: 322 - 327
    • Rolf Drechsler, M. Theobald, Bernd Becker
      Fast FDD based Minimization of Generalized Reed-Muller Forms
      1994 Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen
    • Rolf Drechsler, H. Esbensen, Bernd Becker
      Genetic Algorithms in Computer Aided Design of Integrated Circuits
      , Nummer: 17/94, 1994
    • Bernd Becker, Rolf Drechsler, M. Theobald
      Minimization of 2-level AND/XOR Expressions using Ordered Kronecker Functional Decision Diagrams
      , Nummer: 3/94, 1994
    • Rolf Drechsler, Bernd Becker, A. Jahnke
      On Variable Ordering and Decomposition Type Choice in OKFDDs
      1994 Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen
    • Rolf Drechsler, Bernd Becker, A. Jahnke
      On Variable Ordering and Decomposition Type Choice in OKFDDs
      , Nummer: 11/94, 1994
    • Bernd Becker, Rolf Drechsler, M. Theobald
      On Variable Ordering of Functional Decision Diagrams
      , Nummer: TR-94-006, 1994
    • Bernd Becker, Rolf Drechsler, M. Theobald
      On Variable Ordering of Ordered Functional Decision Diagrams
      1994 GI/GME/ITG-Fachtagung “Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme”, Springer Verlag, Seiten: 62 - 71
    • Rolf Drechsler, A. Sarabi, M. Theobald, Bernd Becker, M. A. Perkowski
      On the Computational Power of Ordered Kronecker Functional Decision Diagrams
      , Nummer: 4/94, 1994
    • Rolf Drechsler, A. Sarabi, M. Theobald, Bernd Becker, M. A. Perkowski
      Ordered Kronecker Functional Decision Diagrams: An Efficient Tool for Synthesis and Verification
      1994 GI/ITG Workshop “Anwendung formaler Methoden im Systementwurf”
    • D. Möller, Paul Molitor, Rolf Drechsler
      Symmetry based Variable Ordering for ROBDDs
      1994 IFIP Workshop on Logic and Architecture Synthesis, Grenoble, Seiten: 47 - 53
    • Bernd Becker, Rolf Drechsler
      Synthesis for Testability: Circuits Derived from Ordered Kronecker Functional Decision Diagrams
      1994 Int'l Test Synthesis Workshop
    • Bernd Becker, Rolf Drechsler
      Synthesis for Testability: Circuits Derived from Ordered Kronecker Functional Decision Diagrams
      , Nummer: 14/94, 1994
    • Harry Hengster, Rolf Drechsler, Bernd Becker
      Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model
      1994 Int'l Conf. on VLSI Design, Seiten: 123 - 126
    • Bernd Becker, Rolf Drechsler
      Testability of Circuits Derived from Functional Decision Diagrams
      1994 European Design and Test Conf., Seite: 667

    1993

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    • Bernd Becker, Rolf Drechsler, Harry Hengster, R. Krieger, R. Sinković
      Binary Decision Diagrams and Testing
      1993 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Rolf Drechsler, A. Sarabi, M. Theobald, Bernd Becker, M. A. Perkowski
      Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams
      , Nummer: 14/93, 1993
    • Rolf Drechsler, M. Theobald, Bernd Becker
      Fast FDD based Minimization of Generalized Reed-Muller Forms
      , Nummer: 15/93, 1993
    • Bernd Becker, Rolf Drechsler, Harry Hengster
      Local Circuit Transformations Preserving Robust Path-Delay-Fault Testability
      , Nummer: 1/93, 1993
    • Bernd Becker, Rolf Drechsler, Paul Molitor
      On Generation of Area-Time Optimal Testable Adders
      1993 Technical Report 3/93
    • Bernd Becker, Rolf Drechsler, M. Theobald
      On Variable Ordering of Functional Decision Diagrams
      , 1993
    • Bernd Becker, Rolf Drechsler
      On the Computational Power of Functional Decision Diagrams
      1993 Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen
    • Bernd Becker, Rolf Drechsler, M. Theobald
      On the Implementation of a Package for Efficient Representation and Manipulation of Functional Decision Diagrams
      1993 IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Seiten: 162 - 169
    • Bernd Becker, Rolf Drechsler, R. Werchner
      On the Relation between BDDs and FDDs
      , Nummer: 12/93, 1993
    • Bernd Becker, Rolf Drechsler, Christoph Meinel
      On the Testability of Circuits Derived from Binary Decision Diagrams
      , Nummer: 9/93, 1993
    • Rolf Drechsler, Bernd Becker
      Rapid Prototyping of Fully Testable Multi-Level AND/EXOR Networks
      1993 IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Seiten: 126 - 133
    • Bernd Becker, Rolf Drechsler
      Testability of Circuits Derived from Functional Decision Diagrams
      , 1993

    1992

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    • Rolf Drechsler, Bernd Becker, Paul Molitor
      A Performance Oriented Generator for Robust Path-Delay-Fault Testable Adders
      1992 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Bernd Becker, Rolf Drechsler, Paul Molitor
      On the Implementation of an Efficient Performance Driven Generator for Conditional-Sum-Adders.
      1992 Technical Report 2/93
    • Rolf Drechsler, Bernd Becker
      Rapid Prototyping of Robust Path-Delay-Fault Testable Circuits Derived from Binary Decision Diagrams
      , Nummer: TR-17/92, SFB 124, 1992