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Name Ilia Polian, Dr. Ilia Polian, Dr.
Adresse Fakultät für angewandte Wissenschaften
Albert-Ludwigs-Universität
Georges Köhler Allee, Gebäude 51
79110 Freiburg im Breisgau
Deutschland
Büro Gebäude 51, Raum 01..030
Telefon ++49 +761 203-8143
Fax ++49 +761 203-8142
eMail polian@informatik.uni-freiburg.de
Website http://ira.informatik.uni-freiburg.de/~polian
Funktion Guru

Ilia Polian

Jahre: 2017 | 2016 | 2015 | 2014 | 2013 | 2012 | 2011 | 2010 | 2009 | 2008 | 2007 | 2006 | 2005 | 2004 | 2003 | 2002 | 2001 | 1999

    2017

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    • Jan Burchard, Maël Gay, Ange-Salomé Messeng Ekossono, Jan Horáček, Bernd Becker, Tobias Schubert, Martin Kreuzer, Ilia Polian
      AutoFault: Towards Automatic Construction of Algebraic Fault Attacks
      2017 Fault Diagnosis and Tolerance in Cryptography (FDTC) 2017
    • Matthias Sauer, Pascal Raiola, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian
      Sensitized Path PUF: A Lightweight Embedded Physical Unclonable Function
      2017 Conf. on Design, Automation and Test in Europe
    • Jan Burchard, Ange-Salomé Messeng Ekossono, Jan Horáček, Maël Gay, Bernd Becker, Tobias Schubert, Martin Kreuzer, Ilia Polian
      Towards Mixed Structural-Functional Models for Algebraic Fault Attacks on Ciphers
      2017 RESCUE Workshop on Reliability, Security and Quality at ETS 2017
    • Jan Burchard, Ange-Salomé Messeng Ekossono, Jan Horáček, Maël Gay, Bernd Becker, Tobias Schubert, Martin Kreuzer, Ilia Polian
      Towards Mixed Structural-Functional Models for Algebraic Fault Attacks on Ciphers
      2017 International Verification and Security Workshop (IVSW) 2017

    2016

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    • Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian
      On Optimal Power-aware Path Sensitization
      2016 2016 25nd IEEE Asian Test Symposium (ATS)
    • Maël Gay, Jan Burchard, Jan Horáček, Ange-Salomé Messeng Ekossono, Tobias Schubert, Bernd Becker, Ilia Polian, Martin Kreuzer
      Small Scale AES Toolbox: Algebraic and Propositional Formulas, Circuit-Implementations and Fault Equations
      2016 FCTRU'16
    • Matthias Sauer, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian
      Utilizing Intrinsic Delay Variability in Complex Digital Circuits for Defining PUF Behavior
      2016 TRUDEVICE Workshop, Dresden

    2015

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    • Linus Feiten, Matthias Sauer, Tobias Schubert, Victor Tomashevich, Ilia Polian, Bernd Becker
      Formal Vulnerability Analysis of Security Components
      2015 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Band: 34, Nummer: 8, Seiten: 1358 - 1369
    • Matthias Sauer, Bernd Becker, Ilia Polian
      PHAETON: A SAT-based Framework for Timing-aware Path Sensitization
      2015 Ieee T Comput, Band: PP, Nummer: 99

    2014

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    • Matthias Sauer, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker
      Variation-Aware Deterministic ATPG
      2014 IEEE European Test Symposium , Seiten: 1 - 6

    2013

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    • Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Victor Tomashevich, Eberhard Böhl, Ilia Polian, Bernd Becker
      #SAT for Vulnerability Analysis of Security Components
      2013 (Workshop-Paper, Informal Proceedings) IEEE European Test Symposium
    • Matthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker
      Efficient SAT-Based Dynamic Compaction and Relaxation for Longest Sensitizable Paths
      2013 Conf. on Design, Automation and Test in Europe, Seiten: 448 - 453
    • Matthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker
      Provably Optimal Test Cube Generation Using Quantified Boolean Formula Solving
      2013 ASP Design Automation Conf.
    • Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker
      SAT-based Analysis of Sensitisable Paths
      2013 IEEE Design & Test of Computers, Band: 30, Nummer: 4, Seiten: 81 - 88
    • Matthias Sauer, Jan Burchard, Tobias Schubert, Ilia Polian, Bernd Becker
      Waveform-Guided Fault Injection by Clock Manipulation
      2013 TRUDEVICE Workshop

    2012

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    • Alexander Czutro, Michael Imhof, Jie Jiang, Abdullah Mumtaz, Matthias Sauer, Bernd Becker, Ilia Polian, Hans-Joachim Wunderlich
      Variation-Aware Fault Grading
      2012 IEEE Asian Test Symp., Seiten: 344 - 349
    • Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Eberhard Böhl, Ilia Polian, Bernd Becker
      #SAT-Based Vulnerability Analysis of Security Components -- A Case Study
      2012 IEEE International Symposium on Defect and Fault Tolerance (DFT), Seiten: 49 - 54
    • Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
      Functional Justification in Sequential Circuits using SAT and Craig Interpolation
      2012 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
      Functional Test of Small-Delay Faults using SAT and Craig Interpolation
      2012 Int'l Test Conf., Seiten: 1 - 8
    • Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker
      Multi-Conditional ATPG using SAT with Preferences
      2012 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker
      Multi-Conditional SAT-ATPG for Power-Droop Testing
      2012 IEEE European Test Symp.
    • Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
      On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints
      2012 Conf. on Design, Automation and Test in Europe, Seiten: 418 - 423
    • Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
      On the Quality of Test Vectors for Post-Silicon Characterization
      2012 IEEE European Test Symp.
    • Alexander Czutro, Matthias Sauer, Tobias Schubert, Ilia Polian, Bernd Becker
      SAT-ATPG Using Preferences for Improved Detection of Complex Defect Mechanisms
      2012 VLSI Test Symp.
    • Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker
      Small-Delay-Fault ATPG with Waveform Accuracy
      2012 Int'l Conf. on CAD, Seiten: 30 - 36

    2011

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    • Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
      On the Optimality of K Longest Path Generation
      2011 Workshop on RTL and High Level Testing
    • Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker
      Estimation of Component Criticality in Early Design Steps
      2011 IEEE Int'l Online Testing Symp., Seiten: 104 - 110
    • Matthias Sauer, Victor Tomashevich, Jörg Müller, Matthew Lewis, Ilia Polian, Bernd Becker, Wolfram Burgard
      An FPGA-Based Framework for Run-time Injection and Analysis of Soft Errors in Microprocessors
      2011 IEEE Int'l Online Testing Symp., Seiten: 182 - 185
    • Matthias Sauer, Jie Jiang, Alexander Czutro, Ilia Polian, Bernd Becker
      Efficient SAT-Based Search for Longest Sensitisable Paths
      2011 Test Symposium (ATS), 2011 20th Asian, Seiten: 108 - 113
    • Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker
      SAT-Based Analysis of Sensitisable Paths
      2011 IEEE Design and Diagnostics of Electronic Circuits and Systems, Seiten: 93 - 98

    2010

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    • Ilia Polian, Bernd Becker
      Fault Models and Test Algorithms for Nanoscale Technologies
      2010 it - Information Technology, Band: 52, Nummer: 4, Seiten: 189 - 194
    • Alexander Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
      Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis
      2010 International Journal of Parallel Programming, Band: 38, Nummer: 3-4, Seiten: 185 - 202
    • Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich
      Variation-Aware Fault Modeling
      2010 IEEE Asian Test Symp., Seiten: 87 - 93

    2009

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    • Alexander Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
      Dynamic Compaction in SAT-Based ATPG
      2009 IEEE Asian Test Symp.
    • Alexander Czutro, Bernd Becker, Ilia Polian
      Performance Evaluation of SAT-Based ATPG on Multi-Core Architectures
      2009 IEEE East-West Design & Test Symposium
    • Marc Hunger, Sybille Hellebrand, Alexander Czutro, Ilia Polian, Bernd Becker
      Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung
      2009 GMM/ITG-Fachtagung “Zuverlässigkeit und Entwurf”
    • Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian
      SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges
      2009 ACM Trans. on Design Automation of Electronic Systems, Band: 14, Nummer: 4, Seiten: 56:1 - 56:21
    • Marc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, Bernd Becker
      ATPG-Based Grading of Strong Fault-Secureness
      2009 IEEE Int'l Online Testing Symp.
    • Nicolas Houarche, Alejandro Czutro, Mariane Comte, Piet Engelke, Ilia Polian, Bernd Becker, Michel Renovell
      An Electrical Model for the Fault Simulation of Small-Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects
      2009 VLSI Test Symp.
    • Nicolas Houarche, Alejandro Czutro, Mariane Comte, Piet Engelke, Ilia Polian, Bernd Becker, Michel Renovell
      Deriving an Electrical Model for Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects
      2009 Latin-American Test Workshop
    • Alejandro Czutro, Bernd Becker, Ilia Polian
      Performance Evaluation of SAT-Based Automatic Test Pattern Generation on Multi-Core Architectures
      2009 GI/ITG Int'l Conf. on Architecture of Computing Systems, Many-Cores Workshop
    • Alejandro Czutro, Bernd Becker, Ilia Polian
      Performance Evaluation of SAT-Based ATPG on Multi-Core Architectures
      2009 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
      TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis
      2009 Int'l Conf. on VLSI Design, Seiten: 227 - 232
    • V. Izosimov, Ilia Polian, P. Pop, P. Eles, Z. Peng
      Analysis and optimization of fault-tolerant embedded systems with hardened processors
      2009 Conf. on Design, Automation and Test in Europe
    • Stefan Hillebrecht, Ilia Polian, P. Ruther, S. Herwik, Bernd Becker, Oliver Paul
      Reliability Characterization of Interconnects in CMOS Integrated Circuits Under Mechanical Stress
      2009 Int'l Reliability Physics Symp.

    2008

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    • Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker
      A Simulator of Small-Delay Faults Caused by Resistive-Open Defects
      2008 IEEE European Test Symp., Seiten: 113 - 118
    • Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
      TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis
      2008 edaWorkshop
    • Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker
      On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
      2008 IEEE Trans. on CAD, Band: 27, Nummer: 2, Seiten: 327 - 338
    • Damian Nowroth, Ilia Polian, Bernd Becker
      A Study of Cognitive Resilience in a JPEG Compressor
      2008 Int'l Conf. on Dependable Systems and Networks, Seiten: 32 - 41
    • Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
      Automatic Test Pattern Generation for Interconnect Open Defects
      2008 VLSI Test Symp., Seiten: 181 - 186
    • Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
      Automatic Test Pattern Generation for Interconnect Open Defects
      2008 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Ilia Polian, Yusuke Nakamura, Piet Engelke, Stefan Hillebrecht, Kohei Miyase, Seiji Kajihara, Bernd Becker, Xiaoqing Wen
      Diagnose realistischer Defekte mit Hilfe des X-Fehlermodells
      2008 GMM/GI/ITG Reliability and Design Conf., Seiten: 155 - 156
    • Ilia Polian, Yusuke Nakamura, Piet Engelke, Stefan Spinner, Kohei Miyase, Seiji Kajihara, Bernd Becker, Xiaoqing Wen
      Diagnosis of Realistic Defects Based on the X-Fault Model
      2008 IEEE Design and Diagnostics of Electronic Circuits and Systems, Seiten: 263 - 268
    • Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
      Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model
      2008 Int'l Test Conf., Seiten: 1 - 10
    • Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, X. Tang, Bernd Becker
      No Free Lunch in Error Protection?
      2008 Workshop on Dependable and Secure Nanocomputing
    • Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, X. Tang, Bernd Becker
      On Reducing Circuit Malfunctions Caused by Soft Errors
      2008 Int'l Symp. on Defect and Fault Tolerance, Seiten: 245 - 253
    • Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker
      Resistive Bridging Fault Simulation of Industrial Circuits
      2008 Conf. on Design, Automation and Test in Europe, Seiten: 628 - 633
    • Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker
      Resistive Bridging Fault Simulation of Industrial Circuits
      2008 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Ilia Polian, Sudhakar M. Reddy, Bernd Becker
      Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors
      2008 IEEE Int'l Symp. on VLSI, Seiten: 257 - 262
    • Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker
      Selective Hardening in Early Design Steps
      2008 IEEE European Test Symp., Seiten: 185 - 190
    • Ilia Polian, W. Rao
      Selective Hardening of NanoPLA Circuits
      2008 Int'l Symp. on Defect and Fault Tolerance, Seiten: 263 - 271

    2007

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    • Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
      Power Droop Testing
      2007 IEEE Design & Test of Computers, Band: 24, Nummer: 3, Seiten: 276 - 284
    • Stefan Spinner, Ilia Polian, Bernd Becker, P. Ruther, Oliver Paul
      A System for the Calibration and Reliability Testing of MEMS Devices Under Mechanical Stress
      2007 VDE Microsystem Technology Congress, Seiten: 861 - 864
    • John P. Hayes, Ilia Polian, Bernd Becker
      An Analysis Framework for Transient-Error Tolerance
      2007 VLSI Test Symp., Seiten: 249 - 255
    • Ilia Polian, John P. Hayes, Bernd Becker
      Cost-Efficient Circuit Hardening Based on Critical Soft Error Rate
      2007 IEEE Workshop on RTL ATPG and DfT
    • Ilia Polian, John P. Hayes, Damian Nowroth, Bernd Becker
      Ein kostenbegrenzter Ansatz zur Reduktion der transienten Fehlerrate
      2007 GMM/GI/ITG Reliability and Design Conf., Seiten: 183 - 184
    • Ilia Polian, Hideo Fujiwara
      Functional Constraints vs. Test Compression in Scan-Based Delay Testing
      2007 Jour. Electronic Testing, Seiten: 445 - 455
    • Ilia Polian, Hideo Fujiwara
      Functional Constraints vs. Test Compression in Scan-Based Delay Testing
      2007 Conf. on Design, Automation and Test in Europe, Band: 23, Nummer: 5, Seiten: 445 - 455
    • Ilia Polian, Damian Nowroth, Bernd Becker
      Identification of Critical Errors in Imaging Applications
      2007 Int'l On-Line Test Symp., Seiten: 201 - 202
    • Piet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker
      SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges
      2007 IEEE Asian Test Symp., Seiten: 433 - 438
    • Stefan Spinner, Jie Jiang, Ilia Polian, Piet Engelke, Bernd Becker
      Simulating Open-Via Defects
      2007 IEEE Asian Test Symp., Seiten: 265 - 270
    • Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich
      Test und Zuverlässigkeit Nanoelektronischer Systeme
      2007 GMM/GI/ITG Reliability and Design Conf., Seiten: 139 - 140

    2006

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    • Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
      Power Droop Testing
      2006 Int'l Conf. on Computer Design, Seiten: 243 - 250
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
      Simulating Resistive Bridging and Stuck-At Faults
      2006 IEEE Trans. on CAD, Band: 25, Nummer: 10, Seiten: 2181 - 2192
    • Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker
      Analyzing the memory effect of resistive open in CMOS random logic
      2006 Int'l Conf. on Design and Test of Integrated Systems in Nanoscale Technology, Seiten: 251 - 256
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
      Automatic Test Pattern Generation for Resistive Bridging Faults
      2006 Jour. Electronic Testing, Band: 22, Nummer: 1, Seiten: 61 - 69
    • Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke
      X-Masking During Logic BIST and Its Impact on Defect Coverage
      2006 IEEE Trans. on VLSI Systems, Band: 14, Nummer: 2, Seiten: 193 - 202
    • Jan Reineke, Björn Wachter, Stephan Thesing, Reinhard Wilhelm, Jochen Eisinger, Ilia Polian, Bernd Becker
      A Definition and Classification of Timing Anomalies
      2006 Int'l Workshop on Worst-Case Execution Time
    • John P. Hayes, Ilia Polian, Bernd Becker
      A Model for Transient Faults in Logic Circuits
      2006 Int'l Design and Test Workshop
    • Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker
      A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency
      2006 IEEE Asian Test Symp., Seiten: 273 - 278
    • Stefan Spinner, M. Doelle, P. Ruther, Ilia Polian, Oliver Paul, Bernd Becker
      A System for Electro-Mechanical Reliability Testing of MEMS Devices
      2006 Int'l Symp. for Testing and Failure Analysis, Seiten: 147 - 152
    • Sandip Kundu, Ilia Polian
      An Improved Technique for Reducing False Alarms Due to Soft Errors
      2006 Int'l On-Line Test Symp., Seiten: 105 - 110
    • Jochen Eisinger, Ilia Polian, Bernd Becker, Alexander Metzner, Stephan Thesing, Reinhard Wilhelm
      Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis
      2006 IEEE Design and Diagnostics of Electronic Circuits and Systems, IEEE Computer Society, Seiten: 15 - 20
    • Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich
      DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems)
      2006 it - Information Technology, Band: 48, Nummer: 5, Seite: 304
    • Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker
      Delta-IddQ Testing of Resistive Short Defects
      2006 IEEE Asian Test Symp., Seiten: 63 - 68
    • Stefan Spinner, J. Bartholomeyczik, Bernd Becker, M. Doelle, Oliver Paul, Ilia Polian, P. Roth, K. Seitz, P. Ruther
      Electromechanical Reliability Testing of Three-Axial Force Sensors
      2006 Design, Test, Integration and Packaging of MEMS/MOEMS, Seiten: 77 - 82
    • Piet Engelke, Ilia Polian, Hans Manhaeve, Bernd Becker
      IddQ Testing of Resistive Bridging Defects
      2006 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 123 - 124
    • Ilia Polian, Bernd Becker, M. Nakasato, S. Ohtake, Hideo Fujiwara
      Low-Cost Hardening of Image Processing Applications Against Soft Errors
      2006 Int'l Symp. on Defect and Fault Tolerance, Seiten: 274 - 279
    • Ilia Polian, Bernd Becker, M. Nakasato, S. Ohtake, Hideo Fujiwara
      Period of Grace: A New Paradigm for Efficient Soft Error Hardening
      2006 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Stefan Spinner, J. Bartholomeyczik, Bernd Becker, M. Doelle, Oliver Paul, Ilia Polian, R. Roth, K. Seitz, P. Ruther
      Reliability Testing of Three-Dimensional Silicon Force Sensors
      2006 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”

    2005

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    • Ilia Polian, Alejandro Czutro, Bernd Becker
      Evolutionary Optimization in Code-Based Test Compression
      2005 Conf. on Design, Automation and Test in Europe, Seiten: 1124 - 1129
    • Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
      Modeling feedback bridging faults with non-zero resistance.
      2005 Jour. Electronic Testing, Band: 21, Nummer: 1, Seiten: 57 - 69
    • John P. Hayes, Ilia Polian, Thomas Fiehn, Bernd Becker
      A Family of Logical Fault Models for Reversible Circuits
      2005 IEEE European Test Symp., Seiten: 65 - 70
    • Ilia Polian, John P. Hayes, Thomas Fiehn, Bernd Becker
      A Family of Logical Fault Models for Reversible Circuits
      2005 IEEE Asian Test Symp., Seiten: 422 - 427
    • Sandip Kundu, Matthew Lewis, Ilia Polian, Bernd Becker
      A Soft Error Emulation System for Logic Circuits
      2005 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 10 - 14
    • Sandip Kundu, Matthew Lewis, Ilia Polian, Bernd Becker
      A Soft Error Emulation System for Logic Circuits
      2005 Conf. on Design of Circuits and Integrated Systems, Seite: 137
    • M. Doelle, Stefan Spinner, P. Ruther, Ilia Polian, Oliver Paul, Bernd Becker
      A System for Determining the Impact of Mechanical Stress on the Reliability of MEMS
      2005 IEEE European Test Symp., Seiten: 57 - 61
    • M. Doelle, Stefan Spinner, P. Ruther, Ilia Polian, Oliver Paul, Bernd Becker
      A System for Determining the Impact of Mechanical Stress on the Reliability of MEMS
      2005 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 88 - 89
    • Ilia Polian, Hideo Fujiwara
      Functional Constraints vs. Test Compression in Scan-Based Delay Testing
      2005 IEEE Int'l GHz/Gbps Test Workshop, Seiten: 91 - 100
    • Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
      Modeling feedback bridging faults with non-zero resistance
      2005 Jour. Electronic Testing, Band: 21, Nummer: 1, Seiten: 57 - 69
    • Ilia Polian
      Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen
      2005 it - Information Technology, Band: 47, Nummer: 3, Seiten: 172 - 174
    • Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker
      On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
      2005 IEEE Asian Test Symp., Seiten: 266 - 269
    • Ilia Polian, Sandip Kundu, Jean-Marc Galliere, Piet Engelke, Michel Renovell, Bernd Becker
      Resistive Bridge Fault Model Evolution From Conventional to Ultra Deep Submicron Technologies
      2005 VLSI Test Symp., Seiten: 343 - 348
    • Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
      Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
      2005 IEEE Design and Diagnostics of Electronic Circuits and Systems, Seiten: 43 - 48
    • Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
      Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
      2005 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 16 - 20
    • Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
      Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
      2005 IEEE Int'l Workshop on Current and Defect-Based Testing, Seiten: 43 - 48
    • Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker
      Transient Fault Characterization in Dynamic Noisy Environments
      2005 Int'l Test Conf., Seiten: 10 pp. - 1048

    2004

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    • Ilia Polian, Bernd Becker, Alejandro Czutro
      Compression Methods for Path Delay Fault Test Pair Sets: A Comparative Study
      2004 IEEE European Test Symp., Seiten: 263 - 264
    • Ilia Polian, Irith Pomeranz, Sudhakar M. Reddy, Bernd Becker
      On the use of maximally dominating faults in n-detection test generation
      2004 IEE Proceedings Computers and Digital Techniques, Band: 151, Nummer: 3, Seiten: 235 - 244
    • Ilia Polian, Bernd Becker
      Scalable Delay Fault BIST For Use With Low-Cost ATE
      2004 Jour. Electronic Testing, Band: 20, Nummer: 2, Seiten: 181 - 197
    • Yuyi Tang, Hans-Joachim Wunderlich, Harald Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
      X-masking during logic BIST and its impact on defect coverage
      2004 IEEE Int'l Workshop on Test Resource Partitioning, Seiten: 442 - 451
    • Ilia Polian
      On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications
      VDI-Verlag, 2004
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
      Automatic test pattern generation for resistive bridging faults
      2004 IEEE European Test Symp., Seiten: 160 - 165
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
      Automatic test pattern generation for resistive bridging faults
      2004 IEEE Int'l Workshop on Current and Defect-Based Testing, Seiten: 89 - 94
    • Bernd Becker, Markus Behle, Friedrich Eisenbrand, Martin Fränzle, Marc Herbstritt, Christian Herde, Jörg Hoffmann, Daniel Kröning, Bernhard Nebel, Ilia Polian, Ralf Wimmer
      Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems
      2004 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Shaker Verlag, Seiten: 65 - 75
    • Ilia Polian
      On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications.
      GI, Band: D-4, Seiten: 169 - 178, 2004
    • John P. Hayes, Ilia Polian, Bernd Becker
      Testing for Missing-Gate Faults in Reversible Circuits
      2004 IEEE Asian Test Symp., Seiten: 100 - 105
    • Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
      The Pros and Cons of Very-Low-Voltage Testing: An Analysis Based on Resistive Short Defects
      2004 VLSI Test Symp., Seiten: 171 - 178
    • Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
      The Pros and Cons of Very-Low-Voltage Testing: An Analytical View
      2004 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 149 - 153
    • Yuyi Tang, Hans-Joachim Wunderlich, Harald Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
      X-masking during logic BIST and its impact on defect coverage
      2004 Int'l Test Conf., Seiten: 442 - 451

    2003

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    • Ilia Polian, Bernd Becker
      Configuring MISR-Based Two-Pattern BIST Using Boolean Satisfiability
      2003 IEEE Design and Diagnostics of Electronic Circuits and Systems, Seiten: 73 - 80
    • Ilia Polian, Bernd Becker, Sudhakar M. Reddy
      Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST
      2003 Conf. on Design, Automation and Test in Europe, Seiten: 1184 - 1185
    • Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
      Modelling Feedback Bridging Faults With Non-Zero Resistance
      2003 European Test Workshop, Seiten: 91 - 96
    • Ilia Polian, Bernd Becker
      Multiple Scan Chain Design for Two-Pattern Testing
      2003 Jour. Electronic Testing, Band: 19, Nummer: 1, Seiten: 37 - 48
    • Ilia Polian, Wolfgang Günther, Bernd Becker
      Pattern-Based Verification of Connections to Intellectual Property Cores
      2003 INTEGRATION, the VLSI Jour., Band: 35, Nummer: 1, Seiten: 25 - 44
    • Ilia Polian, Bernd Becker
      Reducing ATE Cost in System-on-Chip
      2003 IFIP VLSI-SoC, Seiten: 337 - 342
    • Ilia Polian, Bernd Becker
      Reducing ATE Cost in System-on-Chip Test
      2003 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 34 - 37
    • Ilia Polian, Bernd Becker
      Reducing ATE Cost in System-on-Chip Test
      2003 IEEE Int'l Workshop on Test Resource Partitioning
    • J. Bradford, H. Delong, Ilia Polian, Bernd Becker
      Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
      2003 Jour. Electronic Testing, Band: 19, Nummer: 4, Seiten: 387 - 395
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
      Simulating Resistive Bridging Faults
      2003 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 92 - 97
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
      Simulating Resistive Bridging and Stuck-At Faults
      2003 Int'l Test Conf., Seiten: 1051 - 1059
    • Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
      Simulating Resistive Bridging and Stuck-at Faults
      2003 IEEE Int'l Workshop on Current and Defect-Based Testing, Seiten: 49 - 56
    • Ilia Polian, Wolfgang Günther, Bernd Becker
      The Case For 2-POF
      2003 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Seiten: 164 - 173
    • Ilia Polian, Wolfgang Günther, Bernd Becker
      The Case For 2-POF
      2003 IEEE Design and Diagnostics of Electronic Circuits and Systems, Seiten: 291 - 292

    2002

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    • Ilia Polian, Piet Engelke, Bernd Becker
      Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics
      2002 Int'l Symp. on Multi-Valued Logic, Seiten: 216 - 222
    • Ilia Polian, Irith Pomeranz, Bernd Becker
      Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests
      2002 IEEE Asian Test Symp., Seiten: 9 - 14
    • Ilia Polian, Irith Pomeranz, Bernd Becker
      Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests
      2002 European Test Workshop
    • Ilia Polian, Bernd Becker
      Optimal Bandwidth Allocation in Concurrent SoC Test Under Pin Number Constraints
      2002 Workshop on RTL and High Level Testing, Seiten: 12 - 17
    • J. Bradford, H. Delong, Ilia Polian, Bernd Becker
      Realistic Fault Simulation in an Industrial Setting
      2002 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    • Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker
      Sequential n-Detection Criteria: Keep It Simple!
      2002 IEEE Int'l Online Testing Workshop, Seiten: 189 - 190
    • J. Bradford, H. Delong, Ilia Polian, Bernd Becker
      Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
      2002 European Test Workshop, Seiten: 75 - 80
    • Ilia Polian, Bernd Becker
      Stop & Go BIST
      2002 IEEE Int'l Online Testing Workshop, Seiten: 147 - 151

    2001

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    • Ilia Polian, Wolfgang Günther, Bernd Becker
      Efficient Pattern-Based Verification of Connections to Intellectual Property Cores
      2001 IEEE Asian Test Symp., Seiten: 443 - 448
    • Ilia Polian, Wolfgang Günther, Bernd Becker
      Efficient Pattern-Based Verification of Connections to Intellectual Property Cores
      2001 GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, Seiten: I:111 - 120
    • Ilia Polian, Bernd Becker
      Multiple Scan Chain Design for Two-Pattern Testing
      2001 VLSI Test Symp., Seiten: 88 - 93
    • Ilia Polian, Bernd Becker
      Multiple Scan Chain Design for Two-Pattern Testing
      2001 Latin-American Test Workshop, Seiten: 156 - 161
    • Ilia Polian, Bernd Becker
      Multiple Scan Chain Design for Two-Pattern Testing
      2001 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”

    1999

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    • Martin Keim, Ilia Polian, Harry Hengster, Bernd Becker
      A Scalable BIST Architecture for Delay Faults
      1999 European Test Workshop, Seiten: 98 - 103