module flip_flop (out, in, clk);
   input  clk, in;
   output out;
   reg 	  out;

   initial out = 0;
   
   always @(posedge clk) begin
      out = in;      
   end

endmodule // flip_flop

			 
module fsm_struct(clk, coin, clear, w, o, we, oe, dc, ow, oo, oc);

   // interface declaration
   input  clk, coin, clear, w, o, we, oe;
   output dc, ow, oo, oc;
   wire   s1, s0, s1_, s0_, s1_n, s0_n, clear_n, w_n, we_n, oe_n, t1, t2, t3, t4, t5, t6;

   not n1 (s0_n, s0);
   not n2 (s1_n, s1);
   not n3 (clear_n, clear);
   not n4 (w_n, w);
   not n5 (we_n, we);
   not n6 (oe_n, oe);

   and a1 (t1, s1_n, s0_n, coin);
   and a2 (t2, s1_n, s0, clear_n, w_n);
   and a3 (t3, s1, s0_n, we);
   and a4 (t4, s1, s0, oe);
   and a5 (t5, s1_n, s0, clear_n);
   and a6 (ow, s1, s0_n, we_n);
   and a7 (oo, s1, s0, oe_n);
   and a8 (oc, s1_n, s0, clear);
   and a9 (s1_, t5, t6); 
   
   or o1 (t6, w, o);
   or o2 (s0_, t1, t2, t3, t4);
   or o3 (dc, t5, t1, t3, t4);

   flip_flop f1 (s1, s1_, clk);
   flip_flop f2 (s0, s0_, clk);
   
endmodule