module fsm(clk, coin, clear, w, o, we, oe, dc, ow, oo, oc);

   // interface declaration
   input clk, coin, clear, w, o, we, oe;
   output dc, ow, oo, oc;
   reg dc, ow, oo, oc;
   reg [2:0] state, next_state;

   // State definitions
   `define idle   'b00
   `define choose 'b01
   `define water  'b10
   `define orange 'b11

   // initial state
   initial 
      state = `idle;
      
   
   // state register block
   always @(posedge clk) 
      state = next_state;

   // next state logic
   always @(state or coin or clear or w or o or we or oe) begin
      next_state = state;  // default to stay in current state
      case (state)
	`idle : if (coin) next_state = `choose;
	`choose : if (clear) next_state = `idle;
		  else if (w) next_state = `water;
		       else if (o) next_state = `orange;
	`water : if (we) next_state = `choose;
		 else next_state = `idle;
	`orange : if (oe) next_state = `choose;
		  else next_state = `idle;
      endcase // case(state)
   end // always @ (state or coin or clear or w or o or we or oe)

   // output function
   always @(state or coin or clear or w or o or we or oe) begin
      // reset all signals
      case (state)
	`idle : 
	   begin
	      oc = 0;
	      ow = 0;
	      oo = 0;
	      if (coin) dc = 1;
	      else      dc = 0;
	   end
	`choose : 
	   if (clear) begin
	      oc = 1;
	      dc = 0;
	   end // if (clear)
	`water : 
	   if (!we) begin   
	      ow = 1;
	      dc = 0;
	   end // if (!we)
	`orange :
	   if (!oe) 
	      begin
		 oo = 1;
		 dc = 0;
	      end
      endcase
   end // always @ (state or coin or w or o or we or oe)
   
   
endmodule // fsm