library ieee;
use ieee.std_logic_1164.all;


entity interface is
  port( clk,porta2          : in       std_logic;
        portb7_6            : in       std_logic_vector(1 downto 0);        
        portb               : inout    std_logic_vector(5 downto 0);
        porte               : in       std_logic_vector(5 downto 0);
        port0, port1, port2 : out      std_logic_vector(5 downto 0));
end interface;



architecture rtl of interface is  
  signal action: bit;
  signal adresse : std_logic_vector(1 downto 0);

  type state_type is (start, adr, d0, d1, d2, erg);
  signal state, next_state : state_type;
begin



output_logic: process(state)
begin
  case state is
  when start => portb <= "ZZZZZZ";                   
  when adr   => portb <= "ZZZZZZ"; adresse <= portb(1 downto 0); 
  when d0    => portb <= "ZZZZZZ"; port0   <= portb; 
  when d1    => portb <= "ZZZZZZ"; port1   <= portb; 
  when d2    => portb <= "ZZZZZZ"; port2   <= portb; 
  when erg   => portb <= porte;                      
  end case;
end process;


state_logic: process(action)
begin
  if action='1' then
  case state is
  when start => if    portb7_6="11" then                  next_state <= erg;
                elsif portb7_6="01" then                  next_state <= adr;
                elsif portb7_6="10" and adresse="00" then next_state <= d0;
                elsif portb7_6="10" and adresse="01" then next_state <= d1;
                elsif portb7_6="10" and adresse="10" then next_state <= d2;
                else                                      next_state <= start;
                end if;
  when adr   => if    portb7_6="00" then                  next_state <= start;
                else                                      next_state <= adr;
                end if;
  when d0    => if    portb7_6="00" then                  next_state <= start;
                else                                      next_state <= d0;
                end if;
  when d1    => if    portb7_6="00" then                  next_state <= start;
                else                                      next_state <= d1;
                end if;
  when d2    => if    portb7_6="00" then                  next_state <= start;
                else                                      next_state <= d2;
                end if;
  when erg   => if    portb7_6="00" then                  next_state <= start;
                else                                      next_state <= erg;
                end if;
  end case;
  end if;
end process;

state <= next_state;



-- Zähler wird bei jeder Änderung von portb7_6 neu gestartet
-- und zählt dann solange hoch, bis er bei 7 angekommen ist. 
-- Bei Zählstand 6  gibt er action-Signal aus.


process(clk, portb7_6)
  variable zaehler: integer range 0 to 7;
  variable wert: std_logic_vector(1 downto 0);
begin
  if (clk'event and clk='1') then
     wert:=portb7_6;
     if zaehler<7 then zaehler:=zaehler+1; else zaehler:=zaehler; end if;
     if zaehler=6 and porta2='0' then action<='1'; else action<='0'; end if;
  else
    zaehler:=zaehler;
  end if;
  if (portb7_6 = wert) then zaehler:=zaehler; else zaehler:=0; end if;
end process;



end rtl;