Name |

Jahre: 2017 | 2016 | 2015 | 2014 | 2013 | 2012 | 2011 | 2010 | 2009 | 2008 | 2007 | 2006 | 2005 | 2004 | 2003 | 2002 | 2001 | 2000 | 1999 | 1998 | 1997 | 1996 | 1995 | 1994 | 1993 | 1992 | 1991 | 1988 | 1987 | 1986 | 1983

## 2017

nach oben zur Jahresübersicht- Uwe Wagschal, Bernd Becker, Thomas Metz, Thomas Waldvogel, Linus Feiten
**Real-time evaluation of political debates at home and abroad with the Debat-O-Meter**

2017 Berlin*19th General Online Research Conference (GOR)* - Matthias Sauer, Pascal Raiola, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian
**Sensitized Path PUF: A Lightweight Embedded Physical Unclonable Function**

2017*Conf. on Design, Automation and Test in Europe* - Felix Neubauer, Karsten Scheibler, Bernd Becker, Ahmed Mahdi, Martin Fränzle, Tino Teige, Tom Bienmüller, Detlef Fehrer
**Accurate Dead Code Detection in Embedded C Code by Arithmetic Constraint Solving**

2017*GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”* - Pascal Raiola, Dominik Erb, Sudhakar Reddy, Bernd Becker
**Accurate Diagnosis of Interconnect Open Defects based on the Robust Enhanced Aggressor Victim Model**

2017*30th International Conference on VLSI Design* - Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker
**Efficient SAT-Based Generation of Hazard-Activated TSO Tests**

2017*IEEE VLSI Test Symposium (VTS'17)* - Jan Burchard, Felix Neubauer, Pascal Raiola, Dominik Erb, Bernd Becker
**Evaluating the Effectiveness of D-Chains in SAT based ATPG**

2017*IEEE Latin American Test Symposium (LATS'17)* - Jan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker
**Fast and Waveform-Accurate Hazard-Aware SAT-Based TSOF ATPG**

2017*Conference on Design, Automation and Test in Europe* - Linus Feiten, Matthias Sauer, Bernd Becker
**Implementation of Delay-Based PUFs on Altera FPGAs***In: Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment*

2017,*Springer International Publishing*, Seiten: 211 - 235, ISBN: 978-3-319-44318-8

## 2016

nach oben zur Jahresübersicht- Benjamin Völker, Tobias Schubert, Bernd Becker
**iHouse: A Voice-Controlled, Centralized, Retrospective Smart Home**

2016 7th EAI International Conference on Sensor Systems and Software - Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian
**On Optimal Power-aware Path Sensitization**

2016*2016 25nd IEEE Asian Test Symposium (ATS)* - Mathias Soeken, Pascal Raiola, Baruch Sterin, Bernd Becker, Giovanni De Micheli, Matthias Sauer
**SAT-based Combinational and Sequential Dependency Computation**

2016*Haifa Verification Conference (HVC)* - Sebastian Volkmann, Linus Feiten, Christian Zimmermann, Sebastian Sester, Laura Wehle, Bernd Becker
**Digitale Tarnkappe: Anonymisierung in Videoaufnahmen**

2016 INFORMATIK 2016*Gesellschaft für Informatik (GI)*, Heinrich C. Mayr, Martin Pinzger, Band: P-252, Seiten: 413 - 426 - Jan Burchard, Tobias Schubert, Bernd Becker
**Distributed Parallel #SAT Solving**

2016*IEEE Cluster 2016* - Mathias Soeken, Pascal Raiola, Baruch Sterin, Matthias Sauer
**SAT-based Functional Dependency Computation**

2016 International Workshop on Logic & Synthesis - Michael Kochte, Rafal Baranowski, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich
**Formal Verification of Secure Reconfigurable Scan Network Infrastructure**

2016 IEEE European Test Symposium - Michael Kochte, Matthias Sauer, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
**SHIVA: Sichere Hardware in der Informationsverarbeitung Formaler Nachweis komplexer Sicherheitseigenschaften in rekonfigurierbarer Infrastruktur**

2016 eda Workshop - Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
**Effective Generation and Evaluation of Diagnostic SBST Programs**

2016 IEEE VLSI Test Symposium - Linus Feiten, Matthias Sauer, Bernd Becker
**On Metrics to Quantify the Inter-Device Uniqueness of PUFs**

2016 TRUDEVICE Workshop, Dresden - Matthias Sauer, Sven Reimer, Daniel Tille, Karsten Scheibler, Dominik Erb, Ulrike Pfannkuchen, Bernd Becker
**Clock Cycle Aware Encoding for SAT-based Circuit Initialization**

2016 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” - Karsten Scheibler, Dominik Erb, Bernd Becker
**Accurate CEGAR-based ATPG in Presence of Unknown Values for Large Industrial Designs**

2016*Conf. on Design, Automation and Test in Europe* - Felix Neubauer, Karsten Scheibler, Bernd Becker, Ahmed Mahdi, Martin Fränzle, Tino Teige, Tom Bienmüller, Detlef Fehrer
**Accurate Dead Code Detection in Embedded C Code by Arithmetic Constraint Solving**

2016*First International Workshop on Satisfiability Checking and Symbolic Computation - FETOPEN-CSA SC2 Workshop - Affiliated with SYNASC 2016* - Karsten Scheibler, Felix Neubauer, Ahmed Mahdi, Martin Fränzle, Tino Teige, Tom Bienmüller, Detlef Fehrer, Bernd Becker
**Accurate ICP-based Floating-Point Reasoning**

2016*Formal Methods in Computer-Aided Design*, Seiten: 177 - 184 - Ahmed Mahdi, Karsten Scheibler, Felix Neubauer, Martin Fränzle, Bernd Becker
**Advancing software model checking beyond linear arithmetic theories**

2016 12th International Haifa Verification Conference, HVC 2016, Haifa, Israel, November 14-17, 2016*Twelfth Haifa Verification Conference 2016*, Bloem, Roderick, Arbel, Eli (Eds.), Band: 10028, Seiten: 186 - 201 - Karsten Scheibler, Dominik Erb, Bernd Becker
**Applying Tailored Formal Methods to X-ATPG**

2016*GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”* - Thomas Metz, Uwe Wagschal, Thomas Waldvogel, Marko Bachl, Linus Feiten, Bernd Becker
**Das Debat-O-Meter: ein neues Instrument zur Analyse von TV-Duellen**

2016*ZSE Zeitschrift für Staats- und Europawissenschaften*, Band: 14, Nummer: 1, Seiten: 124 - 149 - Ralf Wimmer, Christoph Scholl, Karina Wimmer, Bernd Becker
**Dependency Schemes for DQBF**

2016*Proceedings of the 19th International Conference on Theory and Applications of Satisfiability Testing (SAT)*, Springer, Band: 9710, Seiten: 473 - 489 - Karsten Scheibler, Felix Neubauer, Ahmed Mahdi, Martin Fränzle, Tino Teige, Tom Bienmüller, Detlef Fehrer, Bernd Becker
**Extending iSAT3 with ICP-Contractors for Bitwise Integer Operations**

*AVACS Technical Report, SFB/TR 14 AVACS, Subproject T1*, Band: 116, 2016 - Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
**Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns**

2016*21st Asia and South Pacific Design Automation Conference* -
*Der Andere Verlag***On the Handling of Uncertainty in Test Pattern Generation**

ISBN: 978-3-86247-571-1

Dominik Erb - Marc Pfeifer, Tobias Schubert, Bernd Becker
**PackSens: A Condition and Transport Monitoring System Based on an Embedded Sensor Platform**

2016 7th EAI International Conference on Sensor Systems and Software - Linus Feiten, Sebastian Sester, Christian Zimmermann, Sebastian Volkmann, Laura Wehle, Bernd Becker
**Revocable Anonymisation in Video Surveillance: A "Digital Cloak of Invisibility"***In: Technology and Intimacy: Choice or Coercion*

2016,*Springer International Publishing*, Seiten: 314 - 327, ISBN: 978-3-319-44804-6 - Bernd Becker, Katrin Weber, Linus Feiten
**SMartphones In der LEhre (SMILE)***In: Kreativ, Innovativ, Motivierend - Lehrkonzepte in der Praxis: Der Instructional Development Award (IDA) der Universität Freiburg*

2016,*Universitäts Verlag Webler (UVW)*, Seiten: 117 - 133, ISBN: 978-3-946017-01-1 - Karina Wimmer, Ralf Wimmer, Christoph Scholl, Bernd Becker
**Skolem Functions for DQBF**

2016 Int'l Symposium on Automated Technology for Verification and Analysis (ATVA)*Proceedings of the 14th International Symposium on Automated Technology for Verification and Analysis (ATVA)*, Springer, Band: 9938, Seiten: 395 - 411 - Karina Wimmer, Ralf Wimmer, Christoph Scholl, Bernd Becker
**Skolem Functions for DQBF (Extended Version)**

, 2016 - Maël Gay, Jan Burchard, Jan Horáček, Ange-Salomé Messeng Ekossono, Tobias Schubert, Bernd Becker, Ilia Polian, Martin Kreuzer
**Small Scale AES Toolbox: Algebraic and Propositional Formulas, Circuit-Implementations and Fault Equations**

2016*FCTRU'16* - Linus Feiten, Jonathan Oesterle, Tobias Martin, Matthias Sauer, Bernd Becker
**Systematic Frequency Biases in Ring Oscillator PUFs on FPGAs**

2016*IEEE Transactions on Multi-Scale Computing Systems (TMSCS)*, Band: PP, Nummer: 99 - Ralf Wimmer
**Tagungsband des 19. GI/ITG/GMM-Workshops "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" (MBMV)**

2016*Universität Freiburg / FreiDok*, Seite: 150 - Paolo Marin, Massimno Narizzano, Luca Pulina, Armando Tacchella, Enrico Giunchiglia
**Twelve Years of QBF Evaluations: QSAT Is PSpace-Hard and It Shows**

2016*Fund Inform*, Band: 149, Nummer: 1-2, Seiten: 133 - 158 - Matthias Sauer, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian
**Utilizing Intrinsic Delay Variability in Complex Digital Circuits for Defining PUF Behavior**

2016 TRUDEVICE Workshop, Dresden

## 2015

nach oben zur Jahresübersicht- Jan Burchard, Tobias Schubert, Bernd Becker
**Laissez-Faire Caching for Parallel #SAT Solving**

2015*International Conference on Theory and Applications of Satisfiability Testing*, Band: 9340, Seiten: 46 - 61 - Paolo Marin, Massimo Narizzano, Luca Pulina, Armando Tacchella, Enrico Giunchiglia
**An Empirical Perspective on Ten Years of QBF Solving**

2015 22nd RCRA International Workshop on Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion 2015 (RCRA 2015)*Proceedings of the 22nd RCRA International Workshop on Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion (RCRA 2015)*, CEUR-WS.org, Band: 1451, Seiten: 62 - 75 - Linus Feiten, Tobias Martin, Matthias Sauer, Bernd Becker
**Improving RO-PUF Quality on FPGAs by Incorporating Design-Dependent Frequency Biases**

2015*IEEE European Test Symposium* - Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
**Identification of High Power Consuming Areas with Gate Type and Logic Level Information**

2015*IEEE European Test Symposium* - Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
**On the Automatic Generation of SBST Test Programs for In-Field Test**

2015*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Bettina Braitling, Luis María Ferrer Fioriti, Hassan Hatefi, Ralf Wimmer, Bernd Becker, Holger Hermanns
**Abstraction-based Computation of Reward Measures for Markov Automata**

2015 Mumbai, India*Int'l Conf. Verification, Model Checking, and Abstract Interpretation (VMCAI)*, Band: 8931, Seiten: 172 - 189 - Dominik Erb, Michael A. Kochte, Sven Reimer, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
**Accurate QBF-based Test Pattern Generation in Presence of Unknown Values**

2015*Computer-Aided Design of Integrated Circuits and Systems (TCAD)* - Linus Feiten, Tobias Martin, Matthias Sauer, Bernd Becker
**Analysis and utilisation of deviations in RO-PUFs under altered FPGA designs**

2015 TRUDEVICE Workshop, Grenoble -
*Der Andere Verlag*, Seite: 174**Bekannte Unbekannte - Formale Methoden in Anwesenheit unbekannter Werte**

ISBN: 978-3-86247-569-8

Sven Reimer - Hassan Hatefi, Bettina Braitling, Ralf Wimmer, Luis Maria Ferrer Fioriti, Holger Hermanns, Bernd Becker
**Cost vs. Time in Stochastic Games and Markov Automata**

2015 International Symposium on Dependable Software Engineering: Theory, Tools and Applications (SETTA)*Proc. of SETTA*, Springer-Verlag, Band: 9409, Seiten: 19 - 34 - Tim Quatmann, Nils Jansen, Christian Dehnert, Ralf Wimmer, Erika Ábrahám, Joost-Pieter Katoen
**Counterexamples for Expected Rewards**

2015*Proceedings of the 20th International Symposium on Formal Methods (FM)*, Springer, Band: 9109, Seiten: 435 - 452 - Linus Feiten, Matthias Sauer
**Extracting the RC4 secret key of the Open Smart Grid Protocol (OSGP)**

2015 Industrial Control System Security (ICSS) Workshop - Linus Feiten, Matthias Sauer, Tobias Schubert, Victor Tomashevich, Ilia Polian, Bernd Becker
**Formal Vulnerability Analysis of Security Components**

2015*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)*, Band: 34, Nummer: 8, Seiten: 1358 - 1369 - Ralf Wimmer, Nils Jansen, Erika Ábrahám, Joost-Pieter Katoen
**High-level Counterexamples for Probabilistic Automata**

2015*Log Meth Comput Sci (Logical Methods In Computer Science)*, Band: 11, Nummer: 1:15, Seiten: 1 - 23 - Andreas Riefert, Matthias Sauer, Sudhakar Reddy, Bernd Becker
**Improving Diagnosis Resolution of a Fault Detection Test Set**

2015*VLSI Test Symposium* - Karsten Scheibler, Dominik Erb, Bernd Becker
**Improving Test Pattern Generation in Presence of Unknown Values beyond Restricted Symbolic Logic**

2015*to be published at European Test Symposium (ETS)* - Bernd Becker, Matthias Sauer, Christoph Scholl, Ralf Wimmer
**Modeling Unknown Values in Test and Verification***In: Formal Modeling and Verification of Cyber-Physical Systems (Proceedings of the 1st International Summer School on Methods and Tools for the Design of Digital Systems)*

2015,*Springer*, Rolf Drechsler, Ulrich Kühne, Seiten: 122 - 150, Rolf Drechsler, Ulrich Kühne, ISBN: 978-3-658-09993-0 - Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
**Multi-Cycle Circuit Parameter Independent ATPG for Interconnect Open Defects**

2015*33rd VLSI Test Symposium (VTS)* - Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
**On the Automatic Generation of SBST Test Programs for In-Field Test**

2015*Conf. on Design, Automation and Test in Europe* - Matthias Sauer, Bernd Becker, Ilia Polian
**PHAETON: A SAT-based Framework for Timing-aware Path Sensitization**

2015*Ieee T Comput*, Band: PP, Nummer: 99 - Ralf Wimmer, Karina Gitina, Jennifer Nist, Christoph Scholl, Bernd Becker
**Preprocessing for DQBF**

2015*Proceedings of the 18th International Conference on Theory and Applications of Satisfiability Testing (SAT)*, Springer, Band: 9340, Seiten: 173 - 190 - Karina Gitina, Ralf Wimmer, Sven Reimer, Matthias Sauer, Christoph Scholl, Bernd Becker
**Solving DQBF Through Quantifier Elimination**

2015*Conf. on Design, Automation and Test in Europe* - Karsten Scheibler, Leonore Winterer, Ralf Wimmer, Bernd Becker
**Towards Verification of Artificial Neural Networks**

2015*GI/ITG/GMM Workshop “Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”* - Ernst Moritz Hahn, Holger Hermanns, Ralf Wimmer, Bernd Becker
**Transient Reward Approximation for Continuous-Time Markov Chains**

2015*Ieee T Reliab*, Band: 64, Nummer: 4 - Christian Miller, Paolo Marin, Bernd Becker
**Verification of Partial Designs Using Incremental QBF**

2015*Ai Commun*, Band: 28, Nummer: 2, Seiten: 283 - 307

## 2014

nach oben zur Jahresübersicht- Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
**Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects**

2014*23nd IEEE Asian Test Symposium (ATS)* - Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker
**Incremental Encoding and Solving of Cardinality Constraints**

2014*International Symposium on Automated Technology for Verification and Analysis*, Springer International Publishing, Band: 8837, Seiten: 297 - 313 - Sven Reimer, Matthias Sauer, Paolo Marin, Bernd Becker
**QBF with Soft Variables**

2014*International Workshop on Automated Verification of Critical Systems (AVOCS)* - Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer
**Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization**

2014*International Conference on Design Technology of Integrated Systems In Nanoscale Era (DTIS)* - Matthias Sauer, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker
**Variation-Aware Deterministic ATPG**

2014 IEEE European Test Symposium , Seiten: 1 - 6 - Matthias Sauer, Sven Reimer, Sudhakar M. Reddy, Bernd Becker
**Efficient SAT-based Circuit Initialization for Large Designs**

2014*Int'l Conf. on VLSI Design* - Nils Jansen, Florian Corzilius, Matthias Volk, Ralf Wimmer, Erika Ábrahám, Joost-Pieter Katoen, Bernd Becker
**Accelerating Parametric Probabilistic Verification**

2014*Int'l Conf. on Quantitative Evaluation of Systems (QEST)*, Springer-Verlag, Band: 8657, Seite: 404-420 - Tobias Schubert, Marc Pfeifer, Bernd Becker
**Accurate Controlling of Velocity on a Mobile Robot**

2014 29th International Conference on Computers and Their Applications - Andreas Riefert, Lyl Ciganda, Matthias Sauer, Paolo Bernadi, Matteo Sonza Reorda, Bernd Becker
**An Effective Approach to Automatic Functional Processor Test Generation for Small-Delay Faults**

2014*Conf. on Design, Automation and Test in Europe* - Sreedhar Saseendran Kumar, Jan Wülfing, Joschka Boedecker, Ralf Wimmer, Martin Riedmiller, Bernd Becker, Ulrich Egert
**Autonomous Control of Network Activity**

2014*9th International Meeting on Substrate-Integrated Microelectrode Arrays (MEA)* - Erika Ábrahám, Bernd Becker, Christian Dehnert, Nils Jansen, Joost-Pieter Katoen, Ralf Wimmer
**Counterexample Generation for Discrete-Time Markov Models: An Introductory Survey***In: International School on Formal Methods for the Design of Computer, Communication, and Software Systems (SFM), Advanced Lectures*

2014,*Springer-Verlag*, Seiten: 65 - 121, - Dominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker
**Efficient SMT-based ATPG for Interconnect Open Defects**

2014*Conf. on Design, Automation and Test in Europe* - Dominik Erb, Michael Koche, Matthias Sauer, Stefan Hillebrecht, Tobias Schubert, Hans-Joachim Wunderlich, Bernd Becker
**Exact Logic and Fault Simulation in Presence of Unknowns**

2014*ACM Transactions on Design Automation of Electronic Systems (TODAES)*, Band: 19, Seiten: 28:1 - 28:17 - Christian Dehnert, Nils Jansen, Ralf Wimmer, Erika Ábrahám, Joost-Pieter Katoen
**Fast Debugging of PRISM Models**

2014*Int'l Symp. on Automated Technology for Verfication and Analysis*, Springer-Verlag - Linus Feiten, Andreas Spilla, Matthias Sauer, Tobias Schubert, Bernd Becker
**Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs**

2014*Information Security Journal: A Global Perspective*, Band: 22, Nummer: 5-6, Seiten: 265 - 273 - Karsten Scheibler, Bernd Becker
**Implication Graph Compression inside the SMT Solver iSAT3**

2014 - Ralf Wimmer, Erika Ábrahám
**Maybe or Maybe Not - Contributions to Stochastic Verification***In: Aspekte der Technischen Informatik: Festschrift zum 60. Geburtstag von Bernd Becker*

2014,*Monsenstein und Vannerdat*, Rolf Drechsler, Seiten: 119 - 127, Rolf Drechsler, - Bettina Braitling, Luis María Ferrer Fioriti, Hassan Hatefi, Ralf Wimmer, Bernd Becker, Holger Hermanns
**MeGARA: Menu-based Game Abstraction and Abstraction Refinement of Markov Automata**

2014 International Workshop on Quantitative Aspects of Programming Languages and Systems , Band: EPTCS - Ralf Wimmer, Nils Jansen, Erika Ábrahám, Joost-Pieter Katoen, Bernd Becker
**Minimal Counterexamples for Linear-Time Probabilistic Verification**

2014*Theor Comput Sci* - Nils Jansen, Ralf Wimmer, Erika Ábrahám, Barna Zajzon, Joost-Pieter Katoen, Bernd Becker, Johann Schuster
**Symbolic Counterexample Generation for Large Discrete-Time Markov Chains**

2014*Sci Comput Program*, Band: 91, Nummer: A, Seiten: 90 - 114 - Dominik Erb, Karsten Scheibler, Michael Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
**Test Pattern Generation in Presence of Unknown Values Based on Restricted Symbolic Logic**

2014*Int'l Test Conf.* -
*Der Andere Verlag*, Seite: 184**Testing Time - Time to Test? -- Using Formal Methods for the Timing Analysis of Digital Circuits --**

ISBN: 978-3-86247-451-6

Matthias Sauer - Karsten Scheibler, Bernd Becker
**Using Interval Constraint Propagation for Pseudo-Boolean Constraint Solving**

2014*Formal Methods in Computer-Aided Design* - Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker
**Using MaxBMC for Pareto-Optimal Circuit Initialization**

2014*Conf. on Design, Automation and Test in Europe*

## 2013

nach oben zur Jahresübersicht- Linus Feiten, Katrin Weber, Bernd Becker
**SMILE: Smartphones in der Lehre – ein Rück- und Überblick**

2013 INFORMATIK 2013*Gesellschaft für Informatik (GI)*, Matthias Horbach, Band: P-220, Seiten: 255 - 269 - Tobias Schubert, Jan Burchard, Matthias Sauer, Bernd Becker
**S-Trike: A Mobile Robot Platform for Higher Education**

2013*International Conference on Computer Applications in Industry and Engineering*, Seiten: 243 - 248 - Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Victor Tomashevich, Eberhard Böhl, Ilia Polian, Bernd Becker
**#SAT for Vulnerability Analysis of Security Components**

2013 (Workshop-Paper, Informal Proceedings)*IEEE European Test Symposium* - Ulrich Loup, Karsten Scheibler, Florian Corzilius, Erika Ábrahám, Bernd Becker
**A Symbiosis of Interval Constraint Propagation and Cylindrical Algebraic Decomposition**

2013*CADE*, Springer, Band: 7898, Seiten: 193 - 207 - Nils Jansen, Florian Corzilius, Matthias Volk, Ralf Wimmer, Erika Ábrahám, Joost-Pieter Katoen, Becker, Bernd
**Accelerating Parametric Probabilistic Verification**

*arXiv*, Band: arXiv:1312.3979, 2013 - Benjamin Andres, Matthias Sauer, Martin Gebser, Tobias Schubert, Bernd Becker, Torsten Schaub
**Accurate Computation of Sensitizable Paths using Answer Set Programming**

2013*Int. Conf. on Logic Programming and Nonmonotonic Reasoning*, Seiten: 92 - 101 - Dominik Erb, Michael A Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
**Accurate Multi-Cycle ATPG in Presence of X-Values**

2013*22nd IEEE Asian Test Symposium (ATS)* - Stefan Hillebrecht, Michael A. Kochte, Dominik Erb, Hans-Joachim Wunderlich, Bernd Becker
**Accurate QBF-based test pattern generation in presence of unknown values**

2013*Conf. on Design, Automation and Test in Europe* - Linus Feiten, Andreas Spilla, Matthias Sauer, Tobias Schubert, Bernd Becker
**Analysis of Ring Oscillator PUFs on 60nm FPGAs**

2013 TRUDEVICE Workshop, Avignon - Matthias Sauer, Sven Reimer, Stefan Kupferschmid, Tobias Schubert, Paolo Marin, Bernd Becker
**Applying BMC, Craig Interpolation and MAX-SAT to Functional Justification in Sequential Circuits**

2013*RCRA International Workshop on Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion* - Renatus Derbidge, Linus Feiten, Oliver Conradt, Peter Heusser, Stefan Baumgartner
**Assessment of Shape Changes of Mistletoe Berries: A New Software Approach to Automatize the Parameterization of Path Curve Shaped Contours**

2013*Plos One*, Band: 8, Nummer: 4 - Karsten Scheibler, Matthias Sauer, Kohei Miyase, Bernd Becker
**Controlling Small-Delay Test Power Consumption using Satisfibility Modulo Theory Solving**

2013*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Matthias Sauer, Bernd Becker, Subhasish Mitra
**Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics**

2013*Custom Integrated Circuits Conference*, Seiten: 1 - 4 - Matthias Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung-Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra, Bernd Becker
**Early-Life-Failure Detection using SAT-based ATPG**

2013*Int'l Test Conf.*, Seiten: 1 - 10 - Matthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker
**Efficient SAT-Based Dynamic Compaction and Relaxation for Longest Sensitizable Paths**

2013*Conf. on Design, Automation and Test in Europe*, Seiten: 448 - 453 - Karina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker
**Equivalence Checking for Partial Implementations Revisited**

2013 - Karina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker
**Equivalence Checking of Partial Designs using Dependency Quantified Boolean Formulae**

2013*Int'l Conf. on Computer Design*, IEEE Computer Society, Seiten: 396 - 403 - Katrin Weber, Bernd Becker
**Formative Evaluation des mobilen Classroom-Response-Systems SMILE**

2013*GMW 2013 eLearing*, Seiten: 277 - 289 - Ralf Wimmer, Nils Jansen, Andreas Vorpahl, Erika Ábrahám, Joost-Pieter Katoen, Bernd Becker
**High-Level Counterexamples for Probabilistic Automata**

2013 Springer-Verlag, Band: 8054, Seiten: 18 - 33 - Ralf Wimmer, Nils Jansen, Andreas Vorpahl, Erika Ábrahám, Joost-Pieter Katoen, Bernd Becker
**High-Level Counterexamples for Probabilistic Automata**

, Band: arxiv:1305.5055, 2013 - Andreas Riefert, Joerg Mueller, Matthias Sauer, Wolfram Burgard, Bernd Becker
**Identification of Critical Variables using an FPGA-based Fault Injection Framework**

2013*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Andreas Riefert, Joerg Mueller, Matthias Sauer, Wolfram Burgard, Bernd Becker
**Identification of Critical Variables using an FPGA-based Fault Injection Framework**

2013*VLSI Test Symp.*, Seiten: 1 - 6 - Matthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker
**Provably Optimal Test Cube Generation Using Quantified Boolean Formula Solving**

2013*ASP Design Automation Conf.* - Karsten Scheibler, Stefan Kupferschmid, Bernd Becker
**Recent Improvements in the SMT Solver iSAT**

2013 - Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker
**SAT-based Analysis of Sensitisable Paths**

2013*IEEE Design & Test of Computers*, Band: 30, Nummer: 4, Seiten: 81 - 88 - Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
**Search Space Reduction for Low-Power Test Generation**

2013*22nd IEEE Asian Test Symposium (ATS)* - Bettina Braitling, Ralf Wimmer, Bernd Becker, Erika Ábrahám
**Stochastic Bounded Model Checking: Bounded Rewards and Compositionality**

2013 - Matthias Sauer, Jan Burchard, Tobias Schubert, Ilia Polian, Bernd Becker
**Waveform-Guided Fault Injection by Clock Manipulation**

2013*TRUDEVICE Workshop* -
*Der Andere Verlag*, Seite: 266**Über Craigsche Interpolation und deren Anwendung in der formalen Modellprüfung**

ISBN: 978-3-86247-411-0

Stefan Kupferschmid

## 2012

nach oben zur Jahresübersicht- Alexander Czutro, Michael Imhof, Jie Jiang, Abdullah Mumtaz, Matthias Sauer, Bernd Becker, Ilia Polian, Hans-Joachim Wunderlich
**Variation-Aware Fault Grading**

2012*IEEE Asian Test Symp.*, Seiten: 344 - 349 - Christian Miller, Paolo Marin, Bernd Becker
**A Dynamic QBF Preprocessing Approach for the Verification of Incomplete Designs**

2012*Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion*, Band: 19 - Sven Reimer, Florian Pigorsch, Christoph Scholl, Bernd Becker
**Enhanced Integration of QBF Solving Techniques**

2012 - Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Eberhard Böhl, Ilia Polian, Bernd Becker
**#SAT-Based Vulnerability Analysis of Security Components -- A Case Study**

2012*IEEE International Symposium on Defect and Fault Tolerance (DFT)*, Seiten: 49 - 54 - Bernd Becker, Ruediger Ehlers, Matthew Lewis, Paolo Marin
**ALLQBF Solving by Computational Learning**

2012*Automated Technology for Verification and Analysis*, Springer, Band: 7561, Seiten: 370 - 384 - Benjamin Andres, Matthias Sauer, Martin Gebser, Tobias Schubert, Bernd Becker, Torsten Schaub
**Accurate Computation of Longest Sensitizable Paths using Answer Set Programming**

2012*GMM/ITG-Fachtagung “Zuverlässigkeit und Entwurf”* - Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Sudhakar M. Reddy, Bernd Becker
**Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation**

2012*Int'l Conf. on VLSI Design* - Stefan Hillebrecht, Michael Kochte, Hans-Joachim Wunderlich, Bernd Becker
**Exact Stuck-at Fault Classification in Presence of Unknowns**

2012*IEEE European Test Symp.* - Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
**Functional Justification in Sequential Circuits using SAT and Craig Interpolation**

2012*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
**Functional Test of Small-Delay Faults using SAT and Craig Interpolation**

2012*Int'l Test Conf.*, Seiten: 1 - 8 - Paolo Marin, Christian Miller, Bernd Becker
**Incremental QBF Preprocessing for Partial Design Verification - (Poster Presentation)**

2012*Int'l Conf. on Theory and Applications of Satisfiability Testing*, Springer, Band: 7317, Seiten: 473 - 474 - Ralf Wimmer, Nils Jansen, Erika Ábrahám, Joost-Pieter Katoen, Bernd Becker
**Minimal Counterexamples for Refuting omega-Regular Properties of Markov Decision Processes**

*AVACS Technical Report*, Nummer: 88, 2012 - Ralf Wimmer, Bernd Becker, Nils Jansen, Erika Ábrahám, Joost-Pieter Katoen
**Minimal Critical Subsystems as Counterexamples for omega-Regular DTMC Properties**

2012 - Ralf Wimmer, Bernd Becker, Nils Jansen, Erika Ábrahám, Joost-Pieter Katoen
**Minimal Critical Subsystems for Discrete-Time Markov Models**

2012*Int'l Conf. on Tools and Algorithms for the Construction and Analysis of Systems*, Springer-Verlag, Band: 7214, Seiten: 299 - 314 - Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker
**Multi-Conditional ATPG using SAT with Preferences**

2012*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker
**Multi-Conditional SAT-ATPG for Power-Droop Testing**

2012*IEEE European Test Symp.* - Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
**On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints**

2012*Conf. on Design, Automation and Test in Europe*, Seiten: 418 - 423 - Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
**On the Quality of Test Vectors for Post-Silicon Characterization**

2012*IEEE European Test Symp.* - Alexander Czutro, Matthias Sauer, Tobias Schubert, Ilia Polian, Bernd Becker
**SAT-ATPG Using Preferences for Improved Detection of Complex Defect Mechanisms**

2012*VLSI Test Symp.* - Linus Feiten, Manuel Bührer, Sebastian Sester, Bernd Becker
**SMILE - SMARTPHONES IN LECTURES - Initiating a Smartphone-based Audience Response System as a Student Project**

2012*4th International Conference on Computer Supported Education (CSEDU)*, Seiten: 288 - 293 - Celia Kändler, Linus Feiten, Katrin Weber, Michael Wiedmann, Manuel Bührer, Sebastian Sester, Bernd Becker
**SMILE - smartphones in a university learning environment: a classroom response system**

2012*International Conference of the Learning Sciences (ICLS)*, International Society of the Learning Sciences, Band: 2, Seiten: 515 - 516 - Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker
**Small-Delay-Fault ATPG with Waveform Accuracy**

2012*Int'l Conf. on CAD*, Seiten: 30 - 36 - Nils Jansen, Erika Ábrahám, Barna Zajzon, Ralf Wimmer, Johann Schuster, Joost-Pieter Katoen, Bernd Becker
**Symbolic Counterexample Generation for Discrete-time Markov Chains**

2012*Int'l Symp. on Formal Aspects of Component Software*, Springer-Verlag, Band: 7684, Seiten: 134 - 151 - Ralf Wimmer
**Symbolische Methoden für die probabilistische Verifikation***In: Ausgezeichnete Informatik-Dissertationen*

2012,*Gesellschaft für Informatik*, Stefan Hölldobler et al., Seiten: 271 - 280, Stefan Hölldobler et al., ISBN: 978-3-88579-416-5 - Nils Jansen, Erika Ábrahám, Matthias Volk, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker
**The COMICS Tool - Computing Minimal Counterexamples for DTMCs**

2012*Automated Technology for Verification and Analysis*, Springer-Verlag, Band: 7561, Seiten: 349 - 353 - Nils Jansen, Erika Ábrahám, Maik Scheffler, Matthias Volk, Andreas Vorpahl, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker
**The COMICS Tool - Computing Minimal Counterexamples for DTMCs**

, Band: arxiv:1206.0603, 2012 - Ernst Moritz Hahn, Holger Hermanns, Ralf Wimmer, Bernd Becker
**Transient Reward Approximation for Grids, Crowds, and Viruses**

*arXiv*, Band: arxiv:1212.1251, 2012 - Paolo Marin, Christian Miller, Matthew Lewis, Bernd Becker
**Verification of Partial Designs Using Incremental QBF Solving**

2012*Conf. on Design, Automation and Test in Europe*, Seiten: 623 - 628

## 2011

nach oben zur Jahresübersicht- Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
**On the Optimality of K Longest Path Generation**

2011*Workshop on RTL and High Level Testing* - Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker
**Estimation of Component Criticality in Early Design Steps**

2011*IEEE Int'l Online Testing Symp.*, Seiten: 104 - 110 - Christian Miller, Christoph Scholl, Bernd Becker
**Verifying Incomplete Networks of Timed Automata**

2011 - Matthias Sauer, Victor Tomashevich, Jörg Müller, Matthew Lewis, Ilia Polian, Bernd Becker, Wolfram Burgard
**An FPGA-Based Framework for Run-time Injection and Analysis of Soft Errors in Microprocessors**

2011*IEEE Int'l Online Testing Symp.*, Seiten: 182 - 185 - Pepijn Crouzen, Ernst Moritz Hahn, Holger Hermanns, Abhishek Dhama, Oliver Theel, Ralf Wimmer, Bettina Braitling, Bernd Becker
**Bounded Fairness for Probabilistic Distributed Algorithms**

2011*Int'l Conf. on Application of Concurrency to System Design*, IEEE Computer Society, Seiten: 89 - 97 - Christian Miller, Karina Gitina, Bernd Becker
**Bounded Model Checking of Incomplete Real-time Systems Using Quantified SMT Formulas**

2011*Int'l Workshop on Microprocessor Test and Verification*, Seiten: 22 - 27 - Bettina Braitling, Ralf Wimmer, Bernd Becker, Nils Jansen, Erika Ábrahám
**Counterexample Generation for Markov Chains using SMT-based Bounded Model Checking**

2011*IFIP Int'l Conf. on Formal Methods for Open Object-based Distributed Systems*, Springer-Verlag, Band: 6722, Seiten: 75 - 89 - Stefan Kupferschmid, Bernd Becker
**Craig interpolation in the presence of non-linear constraints**

2011*Formal Modeling and Analysis of Timed Systems*, Springer, Seiten: 240 - 255 - Stefan Kupferschmid, Bernd Becker
**Craigsche Interpolation für Boolesche Kombinationen linearer und nichtlinearer Ungleichungen**

2011 OFFIS-Institut für Informatik, Seiten: 279 - 288 - Matthias Sauer, Jie Jiang, Alexander Czutro, Ilia Polian, Bernd Becker
**Efficient SAT-Based Search for Longest Sensitisable Paths**

2011*Test Symposium (ATS), 2011 20th Asian*, Seiten: 108 - 113 - Nils Jansen, Erika Ábrahám, Jens Katelaan, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker
**Hierarchical Counterexamples for Discrete-Time Markov Chains**

2011*Int'l Symp. on Automated Technology for Verification and Analysis*, Springer-Verlag, Band: 6996, Seiten: 443 - 452 - Nils Jansen, Erika Ábrahám, Jens Katelaan, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker
**Hierarchical Counterexamples for Discrete-Time Markov Chains**

, Band: AIB-2011-11, 2011 - Stefan Kupferschmid, Matthew Lewis, Tobias Schubert, Bernd Becker
**Incremental preprocessing methods for use in BMC**

2011*Formal Methods in System Design*, Band: 39, Seiten: 185 - 204 - Sven Reimer, Florian Pigorsch, Christoph Scholl, Bernd Becker
**Integration of Orthogonal QBF Solving Techniques**

2011*Conf. on Design, Automation and Test in Europe*, Seiten: 149 - 154 - Ernst Althaus, Bernd Becker, Daniel Dumitriu, Stefan Kupferschmid
**Integration of an LP solver into interval constraint propagation**

2011*Int'l Conf. on Combinatorial optimization and applications*, Springer, Seiten: 343 - 356 - Matthew Lewis, Paolo Marin, Tobias Schubert, Massimo Narizzano, Bernd Becker, Enrico Giunchiglia
**Parallel QBF Solving with Advanced Knowledge Sharing**

2011*Fundamenta Informaticae*, Band: 107, Nummer: 2-3, Seiten: 139 - 166 - Erika Ábrahám, Tobias Schubert, Bernd Becker, Martin Fränzle, Christian Herde
**Parallel SAT Solving in Bounded Model Checking**

2011*Journal of Logic and Computation*, Band: 21, Nummer: 1, Seiten: 5 - 21 - Stefan Kupferschmid, Bernd Becker, Tino Teige, Martin Fränzle
**Proof Certificates and Non-linear Arithmetic Constraints**

2011*IEEE Design and Diagnostics of Electronic Circuits and Systems*, Seiten: 429 - 434 - Ralf Wimmer, Ernst Moritz Hahn, Holger Hermanns, Bernd Becker
**Reachability Analysis for Incomplete Networks of Markov Decision Processes**

2011*Int'l Conf. on Formal Methods and Models for Co-Design*, IEEE Computer Society Press, Seiten: 151 - 160 - Matthew Lewis
**SAT, QBF, and Multicore Processors**

Der Andere Verlag, 2011 - Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker
**SAT-Based Analysis of Sensitisable Paths**

2011*IEEE Design and Diagnostics of Electronic Circuits and Systems*, Seiten: 93 - 98 - Bettina Braitling, Ralf Wimmer, Bernd Becker, Nils Jansen, Erika Ábrahám
**SMT-based Counterexample Generation for Markov Chains**

2011 - Andreas Eggers, Evgeny Kruglov, Stefan Kupferschmid, Karsten Scheibler, Tino Teige, Christoph Weidenbach
**Superposition modulo non-linear arithmetic**

2011*Int'l Symp. on Frontiers of Combining Systems*, Springer, Seiten: 119 - 134

## 2010

nach oben zur Jahresübersicht- Christian Miller, Karina Gitina, Christoph Scholl, Bernd Becker
**Bounded Model Checking of Incomplete Networks of Timed Automata**

2010*Int'l Workshop on Microprocessor Test and Verification*, IEEE Computer Society, Band: 11, Seiten: 61 - 66 - Stefan Kupferschmid, Matthew Lewis, Tobias Schubert, Bernd Becker
**Incremental Preprocessing Methods for use in BMC**

2010*Int'l Workshop on Hardware Verification* - Christian Miller, Stefan Kupferschmid, Bernd Becker
**Exploiting Craig Interpolants in Bounded Model Checking for Incomplete Designs**

2010 - Tobias Nopper, Christian Miller, Matthew Lewis, Bernd Becker, Christoph Scholl
**SAT modulo BDD - A Combined Verification Approach for Incomplete Designs**

2010 - Marco Bozzano, Alessandro Cimatti, Joost-Pieter Katoen, Viet Yen Nguyen, Thomas Noll, Marco Roveri, Ralf Wimmer
**A Model Checker for AADL**

2010*Int'l Conf. on CAV*, Springer-Verlag, Band: 6174, Seiten: 562 - 565 - Pepijn Crouzen, Ernst Moritz Hahn, Holger Hermanns, Abhishek Dhama, Oliver Theel, Ralf Wimmer, Bettina Braitling, Bernd Becker
**Bounded Fairness for Probabilistic Distributed Algorithms**

*AVACS Technical Report*, Band: 57, 2010 - Paolo Marin, Enrico Giunchiglia, Massimo Narizzano
**Conflict and Solution Driven Constraint Learning in QBF**

2010*Doctoral Programme CP 2010* - Ralf Wimmer, Bernd Becker
**Correctness Issues of Symbolic Bisimulation Computation for Markov Chains**

2010*Int'l GI/ITG Conference on “Measurement, Modelling and Evaluation of Computing Systems”*, Springer-Verlag, Band: 5987, Seiten: 287 - 301 - Erika Ábrahám, Nils Jansen, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker
**DTMC Model Checking by SCC Reduction**

2010*Int'l Conf. on Quantitative Evaluation of Systems*, IEEE Computer Society, Seiten: 37 - 46 - Christian Miller, Stefan Kupferschmid, Matthew Lewis, Bernd Becker
**Encoding Techniques, Craig Interpolants and Bounded Model Checking for Incomplete Designs**

2010*Theory and Applications of Satisfiability Testing*, Springer, Seiten: 194 - 208 - Natalia Kalinnik, Erika Ábrahám, Tobias Schubert, Ralf Wimmer, Bernd Becker
**Exploiting Different Strategies for the Parallelization of an SMT Solver**

2010 - Ilia Polian, Bernd Becker
**Fault Models and Test Algorithms for Nanoscale Technologies**

2010*it - Information Technology*, Band: 52, Nummer: 4, Seiten: 189 - 194 - Enrico Giunchiglia, Paolo Marin, Massimo Narizzano
**QuBE7.0, System Description**

2010*Journal of Satisfiability*, Band: 7, Nummer: 8, Seiten: 83 - 88 - Ralf Wimmer, Bettina Braitling, Bernd Becker, Ernst Moritz Hahn, Pepijn Crouzen, Holger Hermanns, Abhishek Dhama, Oliver Theel
**Symblicit Calculation of Long-Run Averages for Concurrent Probabilistic Systems**

2010*Int'l Conf. on Quantitative Evaluation of Systems*, IEEE Computer Society, Seiten: 27 - 36 - Ralf Wimmer, Salem Derisavi, Holger Hermanns
**Symbolic Partition Refinement with Automatic Balancing of Time and Space**

2010*Performance Evaluation*, Band: 67, Nummer: 9, Seiten: 815 - 835 - Alexander Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
**Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis**

2010*International Journal of Parallel Programming*, Band: 38, Nummer: 3-4, Seiten: 185 - 202 - Fabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich
**Variation-Aware Fault Modeling**

2010*IEEE Asian Test Symp.*, Seiten: 87 - 93 - Enrico Giunchiglia, Paolo Marin, Massimo Narizzano
**sQueezeBF: An effective preprocessor for QBFs**

2010*Theory and Applications of Satisfiability Testing*, Springer Verlag, Band: 6175, Seiten: 85 - 98

## 2009

nach oben zur Jahresübersicht- Alexander Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
**Dynamic Compaction in SAT-Based ATPG**

2009*IEEE Asian Test Symp.* - Alexander Czutro, Bernd Becker, Ilia Polian
**Performance Evaluation of SAT-Based ATPG on Multi-Core Architectures**

2009*IEEE East-West Design & Test Symposium* - Marc Hunger, Sybille Hellebrand, Alexander Czutro, Ilia Polian, Bernd Becker
**Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung**

2009*GMM/ITG-Fachtagung “Zuverlässigkeit und Entwurf”* - Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian
**SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges**

2009*ACM Trans. on Design Automation of Electronic Systems*, Band: 14, Nummer: 4, Seiten: 56:1 - 56:21 - Natalia Kalinnik, Tobias Schubert, Erika Ábrahám, Ralf Wimmer, Bernd Becker
**Picoso - A Parallel Interval Constraint Solver**

2009*Int'l Conf. on Parallel and Distributed Processing Techniques and Applications*, CSREA Press, Seiten: 473 - 479 - Marc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, Bernd Becker
**ATPG-Based Grading of Strong Fault-Secureness**

2009*IEEE Int'l Online Testing Symp.* - Nicolas Houarche, Alejandro Czutro, Mariane Comte, Piet Engelke, Ilia Polian, Bernd Becker, Michel Renovell
**An Electrical Model for the Fault Simulation of Small-Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects**

2009*VLSI Test Symp.* - Christoph Scholl, Stefan Disch, Florian Pigorsch, Stefan Kupferschmid
**Computing Optimized Representations for Non-convex Polyhedra by Detection and Removal of Redundant Linear Constraints**

2009*Tools and Algorithms for the Construction and Analysis of Systems*, Springer, Band: 5505, Seiten: 383 - 397 - Nicolas Houarche, Alejandro Czutro, Mariane Comte, Piet Engelke, Ilia Polian, Bernd Becker, Michel Renovell
**Deriving an Electrical Model for Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects**

2009*Latin-American Test Workshop* - Alejandro Czutro, Bernd Becker, Ilia Polian
**Performance Evaluation of SAT-Based Automatic Test Pattern Generation on Multi-Core Architectures**

2009*GI/ITG Int'l Conf. on Architecture of Computing Systems, Many-Cores Workshop* - Christian Miller, Tobias Nopper, Christoph Scholl
**Symbolic CTL Model Checking for Incomplete Designs by Selecting Property-Specific Subsets of Local Component Assumptions**

2009 - Alejandro Czutro, Bernd Becker, Ilia Polian
**Performance Evaluation of SAT-Based ATPG on Multi-Core Architectures**

2009*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
**TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis**

2009*Int'l Conf. on VLSI Design*, Seiten: 227 - 232 - V. Izosimov, Ilia Polian, P. Pop, P. Eles, Z. Peng
**Analysis and optimization of fault-tolerant embedded systems with hardened processors**

2009*Conf. on Design, Automation and Test in Europe* - Andreas Eggers, Natalia Kalinnik, Stefan Kupferschmid, Tino Teige
**Challenges in Constraint-Based Analysis of Hybrid Systems**

2009*Recent Advances in Constraints*, Springer, Band: 5655, Seiten: 51 - 65 - Paolo Marin, Matthew Lewis, Massimo Narizzano, Tobias Schubert, Enrico Giunchiglia, Bernd Becker
**Comparison of Knowledge Sharing Strategies in a Parallel QBF Solver**

2009*High-Performance Computing and Simulation Conference*, Seiten: 161 - 167 - Eckard Böde, Marc Herbstritt, Holger Hermanns, Sven Johr, Thomas Peikenkamp, Reza Pulungan, Jan Rakow, Ralf Wimmer, Bernd Becker
**Compositional Dependability Evaluation for Statemate**

2009*IEEE Trans. on Software Engineering*, Band: 35, Nummer: 2, Seiten: 274 - 292 - Ralf Wimmer, Bettina Braitling, Bernd Becker
**Counterexample Generation for Discrete-time Markov Chains using Bounded Model Checking**

2009*Int'l Conf. on Verification, Model Checking and Abstract Interpretation*, Springer-Verlag, Band: 5403, Seiten: 366 - 380 - Matthew Lewis, Tobias Schubert, Bernd Becker
**DPLL-based Reasoning in a Multi-Core Environment**

2009*Int'l Workshop on Microprocessor Test and Verification* - Abhishek Dhama, Oliver Theel, Pepijn Crouzen, Holger Hermanns, Ralf Wimmer, Bernd Becker
**Dependability Engineering of Silent Self-Stabilizing Systems**

2009*Int'l Symp. on Stabilization, Safety, and Security of Distributed Systems*, Springer-Verlag, Band: 5873, Seiten: 238 - 253 - Paolo Marin, Matthew Lewis, Tobias Schubert, Massimo Narizzano, Bernd Becker, Enrico Giunchiglia
**Evaluation of Knowledge Sharing Strategies in a Parallel QBF Solver**

2009*RCRA International Workshop on Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion* - Tobias Schubert, Matthew Lewis, Bernd Becker
**PaMiraXT: Parallel SAT Solving with Threads and Message Passing**

2009*Journal on Satisfiability, Boolean Modeling, and Computation*, Band: 6, Seiten: 203 - 222 - Matthew Lewis, Paolo Marin, Tobias Schubert, Massimo Narizzano, Bernd Becker, Enrico Giunchiglia
**PaQuBE: Distributed QBF Solving with Advanced Knowledge Sharing**

2009*Int'l Conf. on Theory and Applications of Satisfiability Testing*, Band: 5584, Seiten: 509 - 523 - Stefan Kupferschmid, Tino Teige, Bernd Becker, Martin Fränzle
**Proofs of Unsatisfiability for mixed Boolean and Non-linear Arithmetic Constraint Formulae**

2009 - Matthew Lewis, Tobias Schubert, Bernd Becker
**QMiraXT - A Multithreaded QBF Solver**

2009 - Stefan Hillebrecht, Ilia Polian, P. Ruther, S. Herwik, Bernd Becker, Oliver Paul
**Reliability Characterization of Interconnects in CMOS Integrated Circuits Under Mechanical Stress**

2009*Int'l Reliability Physics Symp.*

## 2008

nach oben zur Jahresübersicht- Christoph Scholl, Stefan Disch, Florian Pigorsch, Stefan Kupferschmid
**Using an SMT Solver and Craig Interpolation to Detect and Remove Redundant Linear Constraints in Representations of Non-Convex Polyhedra**

2008*Int'l Workshop on Satisfiability Modulo Theories*, Seiten: 18 - 26 - Andreas Eggers, Natalia Kalinnik, Stefan Kupferschmid, Tino Teige
**Challenges in Constraint-based Analysis of Hybrid Systems**

2008*ERCIM Workshop on Constraint Solving and Constraint Logic Programming* - Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker
**A Simulator of Small-Delay Faults Caused by Resistive-Open Defects**

2008*IEEE European Test Symp.*, Seiten: 113 - 118 - Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
**TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis**

2008*edaWorkshop* - Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker
**On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing**

2008*IEEE Trans. on CAD*, Band: 27, Nummer: 2, Seiten: 327 - 338 - Damian Nowroth, Ilia Polian, Bernd Becker
**A Study of Cognitive Resilience in a JPEG Compressor**

2008*Int'l Conf. on Dependable Systems and Networks*, Seiten: 32 - 41 - Enrico Giunchiglia, Paolo Marin, Massimo Narizzano
**An Effective Preprocessor for QBF pre-reasoning**

2008*Int'l Workshop on Quantification in Constraint Programming* - Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
**Automatic Test Pattern Generation for Interconnect Open Defects**

2008*VLSI Test Symp.*, Seiten: 181 - 186 - Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
**Automatic Test Pattern Generation for Interconnect Open Defects**

2008*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Ilia Polian, Yusuke Nakamura, Piet Engelke, Stefan Hillebrecht, Kohei Miyase, Seiji Kajihara, Bernd Becker, Xiaoqing Wen
**Diagnose realistischer Defekte mit Hilfe des X-Fehlermodells**

2008*GMM/GI/ITG Reliability and Design Conf.*, Seiten: 155 - 156 - Ilia Polian, Yusuke Nakamura, Piet Engelke, Stefan Spinner, Kohei Miyase, Seiji Kajihara, Bernd Becker, Xiaoqing Wen
**Diagnosis of Realistic Defects Based on the X-Fault Model**

2008*IEEE Design and Diagnostics of Electronic Circuits and Systems*, Seiten: 263 - 268 - Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
**Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model**

2008*Int'l Test Conf.*, Seiten: 1 - 10 - Thomas Eschbach, Bernd Becker
**Interactive Circuit Diagram Visualization**

2008*Computer Graphics and Imaging*, ACTA Press, Seiten: 218 - 223 - Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, X. Tang, Bernd Becker
**No Free Lunch in Error Protection?**

2008*Workshop on Dependable and Secure Nanocomputing* - Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, X. Tang, Bernd Becker
**On Reducing Circuit Malfunctions Caused by Soft Errors**

2008*Int'l Symp. on Defect and Fault Tolerance*, Seiten: 245 - 253 - Ralf Wimmer, Alexander Kortus, Marc Herbstritt, Bernd Becker
**Probabilistic Model Checking and Reliability of Results**

2008*IEEE Design and Diagnostics of Electronic Circuits and Systems*, IEEE Computer Science Press, Seiten: 207 - 212 - Bernd Becker, Marc Herbstritt, Natalia Kalinnik, Matthew Lewis, Juri Lichtner, Tobias Nopper, Ralf Wimmer
**Propositional Approximations for Bounded Model Checking of Partial Circuit Designs**

2008*IEEE Int'l Conf. on Computer Design*, IEEE Computer Society Press, Seiten: 52 - 59 - Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker
**Resistive Bridging Fault Simulation of Industrial Circuits**

2008*Conf. on Design, Automation and Test in Europe*, Seiten: 628 - 633 - Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker
**Resistive Bridging Fault Simulation of Industrial Circuits**

2008*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Ilia Polian, Sudhakar M. Reddy, Bernd Becker
**Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors**

2008*IEEE Int'l Symp. on VLSI*, Seiten: 257 - 262 - Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker
**Selective Hardening in Early Design Steps**

2008*IEEE European Test Symp.*, Seiten: 185 - 190 - Ilia Polian, W. Rao
**Selective Hardening of NanoPLA Circuits**

2008*Int'l Symp. on Defect and Fault Tolerance*, Seiten: 263 - 271 - Ralf Wimmer, Salem Derisavi, Holger Hermanns
**Symbolic Partition Refinement with Dynamic Balancing of Time and Space**

2008*Int'l Conf. on Quantitative Evaluation of Systems*, IEEE Computer Science Press, Seiten: 65 - 74 - Bernd Becker, Paul Molitor
**Technische Informatik: Eine einführende Darstellung**

Oldenbourg Wissenschaftsverlag, 2008 - Ralf Wimmer, Alexander Kortus, Marc Herbstritt, Bernd Becker
**The Demand for Reliability in Probabilistic Verification**

2008 - Jochen Eisinger
**Upper Bounds on the Automata Size for Integer and Mixed Real and Integer Linear Arithmetic**

2008*EACSL Annual Conf. on Computer Science Logic*, Springer-Verlag, Seiten: 430 - 444

## 2007

nach oben zur Jahresübersicht- Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
**Power Droop Testing**

2007*IEEE Design & Test of Computers*, Band: 24, Nummer: 3, Seiten: 276 - 284 - Marc Herbstritt, Bernd Becker, Erika Ábrahám, Christian Herde
**On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata**

2007*IEEE Design and Diagnostics of Electronic Circuits and Systems*, IEEE Computer Society, Seiten: 391 - 396 - Matthew Lewis, Tobias Schubert, Bernd Becker
**Multithreaded SAT Solving**

2007*ASP Design Automation Conf.*, Seiten: 926 - 921 - Bernd Becker, Andreas Podelski, Werner Damm, Martin Fränzle, Ernst-Rüdiger Olderog, Reinhard Wilhelm
**SFB/TR 14 AVACS – Automatic Verification and Analysis of Complex Systems (Der Sonderforschungsbereich/Transregio 14 AVACS – Automatische Verifikation und Analyse komplexer Systeme)**

2007*it - Information Technology*, Oldenbourg Wissenschaftsverlag GmbH, Band: 49, Nummer: 2, Seiten: 118 - 126 - Stefan Spinner, Ilia Polian, Bernd Becker, P. Ruther, Oliver Paul
**A System for the Calibration and Reliability Testing of MEMS Devices Under Mechanical Stress**

2007*VDE Microsystem Technology Congress*, Seiten: 861 - 864 - John P. Hayes, Ilia Polian, Bernd Becker
**An Analysis Framework for Transient-Error Tolerance**

2007*VLSI Test Symp.*, Seiten: 249 - 255 - Marc Herbstritt, Vanessa Struve, Bernd Becker
**Application of Lifting in Partial Design Analysis**

2007*Int'l Workshop on Microprocessor Test and Verification*, IEEE Computer Society, Seiten: 33 - 38 - Tobias Nopper, Christoph Scholl, Bernd Becker
**Computation of Minimal Counterexamples by Using Black Box Techniques and Symbolic Methods**

2007*IEEE Int'l Conf. on Computer-Aided Design*, IEEE Computer Society Press, Seiten: 273 - 280 - Ilia Polian, John P. Hayes, Bernd Becker
**Cost-Efficient Circuit Hardening Based on Critical Soft Error Rate**

2007*IEEE Workshop on RTL ATPG and DfT* - Martin Fränzle, Christian Herde, Tino Teige, S. Ratschan, Tobias Schubert
**Efficient Solving of Large Non-Linear Arithmetic Constraint Systems with Complex Boolean Structure**

2007*Journal on Satisfiability, Boolean Modeling, and Computation*, Band: 1, Nummer: 3-4, Seiten: 209 - 236 - Ilia Polian, John P. Hayes, Damian Nowroth, Bernd Becker
**Ein kostenbegrenzter Ansatz zur Reduktion der transienten Fehlerrate**

2007*GMM/GI/ITG Reliability and Design Conf.*, Seiten: 183 - 184 - Ralf Wimmer, Marc Herbstritt, Bernd Becker
**Forwarding, Splitting, and Block Ordering to Optimize BDD-based Bisimulation Computation**

2007 - Ilia Polian, Hideo Fujiwara
**Functional Constraints vs. Test Compression in Scan-Based Delay Testing**

2007*Jour. Electronic Testing*, Seiten: 445 - 455 - Ilia Polian, Hideo Fujiwara
**Functional Constraints vs. Test Compression in Scan-Based Delay Testing**

2007*Conf. on Design, Automation and Test in Europe*, Band: 23, Nummer: 5, Seiten: 445 - 455 - Ilia Polian, Damian Nowroth, Bernd Becker
**Identification of Critical Errors in Imaging Applications**

2007*Int'l On-Line Test Symp.*, Seiten: 201 - 202 - Bernd Becker, Christian Dax, Jochen Eisinger, Felix Klaedtke
**LIRA: Handling Constraints of Linear Arithmetics over the Integers and the Reals**

2007*Int'l Conf. on CAV*, Springer-Verlag, Seiten: 312 - 315 - Christian Dax, Jochen Eisinger, Felix Klaedtke
**Mechanizing the Powerset Construction for Restricted Classes of omega-Automata**

2007*Int'l Symp. on Automated Technology for Verification and Analysis*, Springer-Verlag, Band: 4762, Seiten: 223 - 236 - Christian Dax, Jochen Eisinger, Felix Klaedtke
**Mechanizing the Powerset Construction for Restricted Classes of omega-Automata**

, Nummer: 228, 2007 - Marc Herbstritt, Bernd Becker
**On Combining 01X-Logic and QBF**

2007*Int'l Conf. on Computer Aided Systems Theory*, Springer Verlag, Seiten: 531 - 538 - Ralf Wimmer, Marc Herbstritt, Bernd Becker
**Optimization Techniques for BDD-based Bisimulation Minimization**

2007*Great Lakes Symp. on VLSI*, ACM Press, Seiten: 405 - 410 - Bernd Becker, Jochen Eisinger, Felix Klaedtke
**Parallelization of Decision Procedures for Automatic Structures**

2007*Workshop on Omega-Automata* - Piet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker
**SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges**

2007*IEEE Asian Test Symp.*, Seiten: 433 - 438 - Stefan Spinner, Jie Jiang, Ilia Polian, Piet Engelke, Bernd Becker
**Simulating Open-Via Defects**

2007*IEEE Asian Test Symp.*, Seiten: 265 - 270 - Ralf Wimmer, Alexander Kortus, Marc Herbstritt, Bernd Becker
**Symbolic Model Checking for DTMCs with Exact and Inexact Arithmetic**

*AVACS Technical Report*, Nummer: 30, 2007 - Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich
**Test und Zuverlässigkeit Nanoelektronischer Systeme**

2007*GMM/GI/ITG Reliability and Design Conf.*, Seiten: 139 - 140 - Ralf Wimmer, Holger Hermanns, Marc Herbstritt, Bernd Becker
**Towards Symbolic Stochastic Aggregation**

*AVACS Technical Report*, Nummer: 16, 2007

## 2006

nach oben zur Jahresübersicht- Ralf Wimmer, Tobias Nopper, Marc Herbstritt, Christoph Löffler, Bernd Becker
**Collaborative Exercise Management**

2006*World Conf. on E-Learning in Corporate, Government, Healthcare, and Higher Education*, Association for the Advancement of Computing in Education (AACE), Seiten: 3127 - 3134 - Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
**Power Droop Testing**

2006*Int'l Conf. on Computer Design*, Seiten: 243 - 250 - Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
**Simulating Resistive Bridging and Stuck-At Faults**

2006*IEEE Trans. on CAD*, Band: 25, Nummer: 10, Seiten: 2181 - 2192 - Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker
**Analyzing the memory effect of resistive open in CMOS random logic**

2006*Int'l Conf. on Design and Test of Integrated Systems in Nanoscale Technology*, Seiten: 251 - 256 - Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
**Automatic Test Pattern Generation for Resistive Bridging Faults**

2006*Jour. Electronic Testing*, Band: 22, Nummer: 1, Seiten: 61 - 69 - Erika Ábrahám, Marc Herbstritt, Bernd Becker, Martin Steffen
**Memory-aware Bounded Model Checking for Linear Hybrid Systems**

2006 - Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke
**X-Masking During Logic BIST and Its Impact on Defect Coverage**

2006*IEEE Trans. on VLSI Systems*, Band: 14, Nummer: 2, Seiten: 193 - 202 - Jan Reineke, Björn Wachter, Stephan Thesing, Reinhard Wilhelm, Jochen Eisinger, Ilia Polian, Bernd Becker
**A Definition and Classification of Timing Anomalies**

2006*Int'l Workshop on Worst-Case Execution Time* - John P. Hayes, Ilia Polian, Bernd Becker
**A Model for Transient Faults in Logic Circuits**

2006*Int'l Design and Test Workshop* - Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker
**A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency**

2006*IEEE Asian Test Symp.*, Seiten: 273 - 278 - Stefan Spinner, M. Doelle, P. Ruther, Ilia Polian, Oliver Paul, Bernd Becker
**A System for Electro-Mechanical Reliability Testing of MEMS Devices**

2006*Int'l Symp. for Testing and Failure Analysis*, Seiten: 147 - 152 - Erika Ábrahám, Andreas Grüner, Martin Steffen
**Abstract Interface Behavior of Object-Oriented Languages with Monitors**

2006*IFIP Int'l Conf. on Formal Methods for Open Object-based Distributed Systems*, Springer-Verlag, Band: 4036, Seiten: 218 - 232 - Marc Herbstritt, Bernd Becker, Christoph Scholl
**Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs**

2006*Int'l Workshop on Microprocessor Test and Verification*, IEEE Computer Society, Seiten: 37 - 44 - Sandip Kundu, Ilia Polian
**An Improved Technique for Reducing False Alarms Due to Soft Errors**

2006*Int'l On-Line Test Symp.*, Seiten: 105 - 110 - Marc Herbstritt, Ralf Wimmer, Thomas Peikenkamp, Eckard Böde, Michael Adelaide, Sven Johr, Holger Hermanns, Bernd Becker
**Analysis of Large Safety-Critical Systems: A quantitative Approach**

*AVACS Technical Report*, Band: 8, 2006 - Jochen Eisinger, Ilia Polian, Bernd Becker, Alexander Metzner, Stephan Thesing, Reinhard Wilhelm
**Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis**

2006*IEEE Design and Diagnostics of Electronic Circuits and Systems*, IEEE Computer Society, Seiten: 15 - 20 - Erika Ábrahám, Marc Herbstritt, Bernd Becker, Martin Steffen
**Bounded Model Checking with Parametric Data Structures**

2006*BMC*, Band: 174, Nummer: 3, Seiten: 3 - 16 - Eckard Böde, Marc Herbstritt, Holger Hermanns, Sven Johr, Thomas Peikenkamp, Reza Pulungan, Ralf Wimmer, Bernd Becker
**Compositional Performability Evaluation for STATEMATE**

2006*Int'l Conf. on Quantitative Evaluation of Systems*, IEEE Computer Society, Seiten: 167 - 178 - Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich
**DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems)**

2006*it - Information Technology*, Band: 48, Nummer: 5, Seite: 304 - Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker
**Delta-IddQ Testing of Resistive Short Defects**

2006*IEEE Asian Test Symp.*, Seiten: 63 - 68 - Jochen Eisinger, Felix Klaedtke
**Don't Care Words with an Application to the Automata-based Approach for Real Addition**

2006*Conf. on Computer Aided Verification*, Band: 4144, Seiten: 67 - 80 - Jochen Eisinger, Felix Klaedtke
**Don't Care Words with an Application to the Automata-based Approach for Real Addition**

, Nummer: 223, 2006 - Erika Ábrahám, Andreas Grüner, Martin Steffen
**Dynamic Heap-Abstraction for Open Object-Oriented Systems with Thread Classes**

, Nummer: TR-0601, 2006 - Stefan Spinner, J. Bartholomeyczik, Bernd Becker, M. Doelle, Oliver Paul, Ilia Polian, P. Roth, K. Seitz, P. Ruther
**Electromechanical Reliability Testing of Three-Axial Force Sensors**

2006*Design, Test, Integration and Packaging of MEMS/MOEMS*, Seiten: 77 - 82 - Piet Engelke, Ilia Polian, Hans Manhaeve, Bernd Becker
**IddQ Testing of Resistive Bridging Defects**

2006*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”*, Seiten: 123 - 124 - Erika Ábrahám, Frank S. de Boer, Willem-Paul de Roever, Martin Steffen
**Inductive Proof Outlines for Exceptions in Multithreaded Java**

2006*IPM Int'l Workshop on Foundations of Software Engineering*, Band: 159, Seiten: 281 - 279 - Martin Fränzle, Christian Herde, S. Ratschan, Tobias Schubert, Tino Teige
**Interval Constraint Solving Using Propositional SAT Solving Techniques**

2006*Int'l Workshop on the Integration of SAT and CP Techniques*, Seiten: 81 - 95 - Ilia Polian, Bernd Becker, M. Nakasato, S. Ohtake, Hideo Fujiwara
**Low-Cost Hardening of Image Processing Applications Against Soft Errors**

2006*Int'l Symp. on Defect and Fault Tolerance*, Seiten: 274 - 279 - Ralf Wimmer, Marc Herbstritt, Bernd Becker
**Minimization of Large State Spaces using Symbolic Branching Bisimulation**

2006*IEEE Design and Diagnostics of Electronic Circuits and Systems*, IEEE Computer Society Press, Seiten: 9 - 14 - Thomas Eschbach, Wolfgang Günther, Bernd Becker
**Orthogonal Hypergraph Drawing for Improved Visibility**

2006*Journal of Graph Algorithms and Applications*, Band: 10, Nummer: 2, Seiten: 141 - 157 - Erika Ábrahám, Tobias Schubert, Bernd Becker, Martin Fränzle, Christian Herde
**Parallel SAT-Solving in Bounded Model Checking**

2006*Int'l Workshop on Parallel and Distributed Methods in Verification*, Springer-Verlag, Band: 4346, Seiten: 301 - 315 - Ilia Polian, Bernd Becker, M. Nakasato, S. Ohtake, Hideo Fujiwara
**Period of Grace: A New Paradigm for Efficient Soft Error Hardening**

2006*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Stefan Spinner, J. Bartholomeyczik, Bernd Becker, M. Doelle, Oliver Paul, Ilia Polian, R. Roth, K. Seitz, P. Ruther
**Reliability Testing of Three-Dimensional Silicon Force Sensors**

2006*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Ralf Wimmer, Marc Herbstritt, Holger Hermanns, Kelley Strampp, Bernd Becker
**Sigref - A Symbolic Bisimulation Tool Box**

2006*Int'l Symp. on Automated Technology for Verification and Analysis*, Springer-Verlag, Band: 4218, Seiten: 477 - 492

## 2005

nach oben zur Jahresübersicht- Marc Herbstritt, Bernd Becker
**On SAT-based Bounded Invariant Checking of Blackbox Designs**

2005*Int'l Workshop on Microprocessor Test and Verification*, IEEE Computer Society, Seiten: 23 - 28 - Martina Welte, Thomas Eschbach, Bernd Becker
**Automated Text Extraction And Indexing Of Video Presentation Recordings For Keyword Search Via A Web Interface**

2005*Workshop eLectures - Einsatzmöglichkeiten, Herausforderungen und Forschungsperspektiven*, Logos Verlag Berlin - Matthew Lewis, Tobias Schubert, Bernd Becker
**Speedup Techniques Utilized in Modern SAT Solvers - An Analysis in the MIRA Environment**

2005*Theory and Applications of Satisfiability Testing*, Springer, Band: 3569, Seiten: 437 - 443 - Ilia Polian, Alejandro Czutro, Bernd Becker
**Evolutionary Optimization in Code-Based Test Compression**

2005*Conf. on Design, Automation and Test in Europe*, Seiten: 1124 - 1129 - Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
**Modeling feedback bridging faults with non-zero resistance.**

2005*Jour. Electronic Testing*, Band: 21, Nummer: 1, Seiten: 57 - 69 - John P. Hayes, Ilia Polian, Thomas Fiehn, Bernd Becker
**A Family of Logical Fault Models for Reversible Circuits**

2005*IEEE European Test Symp.*, Seiten: 65 - 70 - Ilia Polian, John P. Hayes, Thomas Fiehn, Bernd Becker
**A Family of Logical Fault Models for Reversible Circuits**

2005*IEEE Asian Test Symp.*, Seiten: 422 - 427 - Tobias Schubert, Bernd Becker
**A Hardware Lab Anywhere at Any Time**

2005*Journal of Systemics, Cybernetics, and Informatics: JSCI*, Band: 2, Nummer: 6 - Sandip Kundu, Matthew Lewis, Ilia Polian, Bernd Becker
**A Soft Error Emulation System for Logic Circuits**

2005*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”*, Seiten: 10 - 14 - Sandip Kundu, Matthew Lewis, Ilia Polian, Bernd Becker
**A Soft Error Emulation System for Logic Circuits**

2005*Conf. on Design of Circuits and Integrated Systems*, Seite: 137 - M. Doelle, Stefan Spinner, P. Ruther, Ilia Polian, Oliver Paul, Bernd Becker
**A System for Determining the Impact of Mechanical Stress on the Reliability of MEMS**

2005*IEEE European Test Symp.*, Seiten: 57 - 61 - M. Doelle, Stefan Spinner, P. Ruther, Ilia Polian, Oliver Paul, Bernd Becker
**A System for Determining the Impact of Mechanical Stress on the Reliability of MEMS**

2005*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”*, Seiten: 88 - 89 - Tobias Schubert, Bernd Becker
**Accelerating Boolean SAT Engines Using Hyper-Threading Technology**

2005*Asian Applied Computing Conf.* - Erika Ábrahám, Andreas Grüner, Martin Steffen
**An Open Structural Operational Semantics for an Object-Oriented Calculus with Thread Classes**

, Nummer: TR-0505, 2005 - Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker
**An Unified Fault Model and Test Generation Procedure for Interconnect Opens and Bridges**

2005*IEEE European Test Symp.*, Seiten: 22 - 27 - Martina Welte, Thomas Eschbach, Bernd Becker
**Automated Text Extraction And Indexing Of Video Presentation Recordings For Keyword Search Via A Web Interface**

2005*AACE World Conf. on E-Learning in Corporate, Government, Healthcare, and Higher Education*, AACE Press, Seiten: 3200 - 3205 - Bernd Becker, Markus Behle, Friedrich Eisenbrand, Ralf Wimmer
**BDDs in a Branch & Cut Framework**

2005*Int'l Workshop on Efficient and Experimental Algorithms*, Springer Verlag, Band: 3503, Seiten: 452 - 463 - Ilia Polian, Hideo Fujiwara
**Functional Constraints vs. Test Compression in Scan-Based Delay Testing**

2005*IEEE Int'l GHz/Gbps Test Workshop*, Seiten: 91 - 100 - Erika Ábrahám, Andreas Grüner, Martin Steffen
**Heap-Abstraction for an Object-Oriented Calculus with Thread Classes**

, Nummer: TR-0505, 2005 - Tobias Schubert, Bernd Becker
**Knowledge Sharing in a Microcontroller based Parallel SAT Solver**

2005*Int'l Conf. on Parallel and Distributed Processing Techniques and Applications* - Tobias Schubert, Bernd Becker
**Lemma Exchange in a Microcontroller based Parallel SAT Solver**

2005*IEEE Int'l Symp. on VLSI* - Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
**Modeling feedback bridging faults with non-zero resistance**

2005*Jour. Electronic Testing*, Band: 21, Nummer: 1, Seiten: 57 - 69 - Ilia Polian
**Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen**

2005*it - Information Technology*, Band: 47, Nummer: 3, Seiten: 172 - 174 - Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker
**On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing**

2005*IEEE Asian Test Symp.*, Seiten: 266 - 269 - Erika Ábrahám, Bernd Becker, Felix Klaedtke, Martin Steffen
**Optimizing bounded model checking for linear hybrid systems**

2005*Int'l Conf. on Verification, Model Checking and Abstract Interpretation*, Springer-Verlag, Band: 3385, Seiten: 396 - 412 - Thomas Eschbach, Wolfgang Günther, Bernd Becker
**Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases**

2005*Int'l Conf. on VLSI Design*, Seiten: 433 - 438 - Tobias Schubert, Bernd Becker, Matthew Lewis
**PaMira - A Parallel SAT Solver with Knowledge Sharing**

2005*Int'l Workshop on Microprocessor Test and Verification*, IEEE Computer Society, Band: 00, Seiten: 29 - 36 - Ilia Polian, Sandip Kundu, Jean-Marc Galliere, Piet Engelke, Michel Renovell, Bernd Becker
**Resistive Bridge Fault Model Evolution From Conventional to Ultra Deep Submicron Technologies**

2005*VLSI Test Symp.*, Seiten: 343 - 348 - Jochen Eisinger, Peter Winterer, Bernd Becker
**Securing Wireless Networks in a University Environment**

2005*IEEE Int'l Conf. on Pervasive Computing and Communications Workshops*, IEEE Computer Society, Seiten: 312 - 316 - Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
**Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST**

2005*IEEE Design and Diagnostics of Electronic Circuits and Systems*, Seiten: 43 - 48 - Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
**Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST**

2005*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”*, Seiten: 16 - 20 - Piet Engelke, Valentin Gherman, Ilia Polian, Yuyi Tang, Hans-Joachim Wunderlich, Bernd Becker
**Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST**

2005*IEEE Int'l Workshop on Current and Defect-Based Testing*, Seiten: 43 - 48 - Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker
**Transient Fault Characterization in Dynamic Noisy Environments**

2005*Int'l Test Conf.*, Seiten: 10 pp. - 1048

## 2004

nach oben zur Jahresübersicht- Erika Ábrahám, Bernd Becker, Felix Klaedtke, Martin Steffen
**Optimizing Bounded Model Checking for Linear Hybrid Systems**

, Nummer: 214, 2004 - Marc Herbstritt, Thomas Kmieciak, Bernd Becker
**On the Impact of Structural Circuit Partitioning on SAT-based Combinational Circuit Verification**

2004*Int'l Workshop on Microprocessor Test and Verification*, IEEE Computer Society, Seiten: 50 - 55 - Marc Herbstritt, Thomas Kmieciak, Bernd Becker
**Circuit Partitioning for SAT-based Combinational Circuit Verification -- A Case Study**

, Nummer: 206, 2004 - Ilia Polian, Bernd Becker, Alejandro Czutro
**Compression Methods for Path Delay Fault Test Pair Sets: A Comparative Study**

2004*IEEE European Test Symp.*, Seiten: 263 - 264 - Matthew Lewis, Tobias Schubert, Bernd Becker
**Early Conflict Detection Based BCP for SAT Solving**

2004*Int'l Conf. on Theory and Applications of Satisfiability Testing*, Seiten: 29 - 36 - Ilia Polian, Irith Pomeranz, Sudhakar M. Reddy, Bernd Becker
**On the use of maximally dominating faults in n-detection test generation**

2004*IEE Proceedings Computers and Digital Techniques*, Band: 151, Nummer: 3, Seiten: 235 - 244 - Ilia Polian, Bernd Becker
**Scalable Delay Fault BIST For Use With Low-Cost ATE**

2004*Jour. Electronic Testing*, Band: 20, Nummer: 2, Seiten: 181 - 197 - Yuyi Tang, Hans-Joachim Wunderlich, Harald Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
**X-masking during logic BIST and its impact on defect coverage**

2004*IEEE Int'l Workshop on Test Resource Partitioning*, Seiten: 442 - 451 - Ilia Polian
**On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications**

VDI-Verlag, 2004 - Tobias Schubert, Bernd Becker
**A Distributed SAT Solver for Microchip Microcontroller**

2004*Workshop on Parallel Systems and Algorithms* - Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
**Automatic test pattern generation for resistive bridging faults**

2004*IEEE European Test Symp.*, Seiten: 160 - 165 - Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
**Automatic test pattern generation for resistive bridging faults**

2004*IEEE Int'l Workshop on Current and Defect-Based Testing*, Seiten: 89 - 94 - Bernd Becker, Markus Behle, Friedrich Eisenbrand, Martin Fränzle, Marc Herbstritt, Christian Herde, Jörg Hoffmann, Daniel Kröning, Bernhard Nebel, Ilia Polian, Ralf Wimmer
**Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems**

2004 - Matthew Lewis, Tobias Schubert, Bernd Becker
**Early Conflict Detection Based SAT Solving**

2004 - Ilia Polian
**On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications.**

GI, Band: D-4, Seiten: 169 - 178, 2004 - Thomas Eschbach, Wolfgang Günther, Bernd Becker
**Orthogonal Hypergraph Routing for Improved Visibility**

2004*Great Lakes Symp. on VLSI*, Seiten: 385 - 388 - Tobias Schubert, Bernd Becker
**PICHAFF2 - A Hierarchical Parallel SAT Solver**

2004*Int'l Workshop on Microprocessor Test and Verification* - Tobias Schubert, Bernd Becker
**Parallel SAT Solving with Microcontrollers**

2004*Asian Applied Computing Conf.* - Thomas Eschbach, Rolf Drechsler, Bernd Becker
**Placement and Routing Optimization for Circuits Derived from BDDs**

2004*IEEE Int'l Symp. on Circuits and Systems*, Seiten: V229 - V232 - John P. Hayes, Ilia Polian, Bernd Becker
**Testing for Missing-Gate Faults in Reversible Circuits**

2004*IEEE Asian Test Symp.*, Seiten: 100 - 105 - Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
**The Pros and Cons of Very-Low-Voltage Testing: An Analysis Based on Resistive Short Defects**

2004*VLSI Test Symp.*, Seiten: 171 - 178 - Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
**The Pros and Cons of Very-Low-Voltage Testing: An Analytical View**

2004*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”*, Seiten: 149 - 153 - Yuyi Tang, Hans-Joachim Wunderlich, Harald Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
**X-masking during logic BIST and its impact on defect coverage**

2004*Int'l Test Conf.*, Seiten: 442 - 451

## 2003

nach oben zur Jahresübersicht- Tobias Schubert, Bernd Becker
**PICHAFF: A Distributed SAT Solver for Microcontrollers**

2003*Euromicro Conf.* - Thomas Eschbach, Wolfgang Günther, Bernd Becker
**Crossing Reduction for Orthogonal Circuit Visualization**

2003*Int'l Conf. on VLSI*, CSREA Press, Seiten: 107 - 113 - Matthew Lewis, S. Simmons
**A VLSI Implementation of a Cryptographic Processor**

2003*CCECE*, Band: 2, Seiten: 821 - 826 - Marc Herbstritt, Bernd Becker
**Conflict-based Selection of Branching Rules**

2003*Int'l Conf. on Theory and Applications of Satisfiability Testing*, Springer, Band: 2919, Seiten: 441 - 451 - Marc Herbstritt, Bernd Becker
**Conflict-based Selection of Branching Rules in SAT-Algorithms**

2003 - Tobias Schubert, Bernd Becker
**A Hardware Lab Anywhere At Anytime**

2003*Int'l Conf. on Education and Information Systems: Technologies and Applications*, Seiten: 130 - 135 - Andreas Hett, Tobias Schubert
**A Hardware Lab in a Pocket**

2003*World Conf. on E-Learning in Corporate, Government, Healthcare, and Higher Education* - Tobias Schubert, Andreas Hett
**A Hardware Lab in a Pocket**

2003*Int'l Conf. on Multimedia and Information and Communication Technologies in Education* - Ilia Polian, Bernd Becker
**Configuring MISR-Based Two-Pattern BIST Using Boolean Satisfiability**

2003*IEEE Design and Diagnostics of Electronic Circuits and Systems*, Seiten: 73 - 80 - Tobias Schubert, Bernd Becker
**Das Mobile Hardware-Praktikum**

2003*European Conf. on Media in Higher Education* - Ilia Polian, Bernd Becker, Sudhakar M. Reddy
**Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST**

2003*Conf. on Design, Automation and Test in Europe*, Seiten: 1184 - 1185 - Frank Schmiedle, Rolf Drechsler, Bernd Becker
**Exact Routing with Search Space Reduction**

2003*IEEE Trans. on Computers*, Band: 52, Nummer: 6, Seiten: 815 - 825 - Frank Schmiedle
**Exakte Verdrahtung mit symbolischen Methoden**

Logos Verlag, Berlin, 2003 - Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
**Modelling Feedback Bridging Faults With Non-Zero Resistance**

2003*European Test Workshop*, Seiten: 91 - 96 - Ilia Polian, Bernd Becker
**Multiple Scan Chain Design for Two-Pattern Testing**

2003*Jour. Electronic Testing*, Band: 19, Nummer: 1, Seiten: 37 - 48 - Ilia Polian, Wolfgang Günther, Bernd Becker
**Pattern-Based Verification of Connections to Intellectual Property Cores**

2003*INTEGRATION, the VLSI Jour.*, Band: 35, Nummer: 1, Seiten: 25 - 44 - Martin Keim, M. Martin, Bernd Becker, Rolf Drechsler, Paul Molitor
**Polynomial Formal Verification of Multipliers**

2003*Formal Methods in System Design*, Band: 22, Nummer: 1, Seiten: 39 - 58 - Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, L. Linhard, G. Angst
**Recursive Bi-Partitioning of Netlists for Large Number of Partitions**

2003*Journal of Systems Architecture*, Band: 49, Nummer: 12-15, Seiten: 521 - 528 - Ilia Polian, Bernd Becker
**Reducing ATE Cost in System-on-Chip**

2003*IFIP VLSI-SoC*, Seiten: 337 - 342 - Ilia Polian, Bernd Becker
**Reducing ATE Cost in System-on-Chip Test**

2003*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”*, Seiten: 34 - 37 - Ilia Polian, Bernd Becker
**Reducing ATE Cost in System-on-Chip Test**

2003*IEEE Int'l Workshop on Test Resource Partitioning* - J. Bradford, H. Delong, Ilia Polian, Bernd Becker
**Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting**

2003*Jour. Electronic Testing*, Band: 19, Nummer: 4, Seiten: 387 - 395 - Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
**Simulating Resistive Bridging Faults**

2003*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”*, Seiten: 92 - 97 - Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
**Simulating Resistive Bridging and Stuck-At Faults**

2003*Int'l Test Conf.*, Seiten: 1051 - 1059 - Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
**Simulating Resistive Bridging and Stuck-at Faults**

2003*IEEE Int'l Workshop on Current and Defect-Based Testing*, Seiten: 49 - 56 - Ilia Polian, Wolfgang Günther, Bernd Becker
**The Case For 2-POF**

2003 - Ilia Polian, Wolfgang Günther, Bernd Becker
**The Case For 2-POF**

2003*IEEE Design and Diagnostics of Electronic Circuits and Systems*, Seiten: 291 - 292

## 2002

nach oben zur Jahresübersicht- Christoph Scholl, Bernd Becker
**Checking Equivalence for Circuits Containing Incompletely Specified Boxes**

2002*Int'l Conf. on Computer Design*, Seite: 56 - Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker
**Crossing Reduction by Windows Optimization**

2002*Int'l Symp. on Graph Drawing*, Band: 2528, Seiten: 285 - 294 - Ilia Polian, Piet Engelke, Bernd Becker
**Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics**

2002*Int'l Symp. on Multi-Valued Logic*, Seiten: 216 - 222 - Christoph Scholl, Bernd Becker
**Equivalence Checking in the Presence of Incompletely Specified Boxes**

2002 - Ilia Polian, Irith Pomeranz, Bernd Becker
**Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests**

2002*IEEE Asian Test Symp.*, Seiten: 9 - 14 - Ilia Polian, Irith Pomeranz, Bernd Becker
**Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests**

2002*European Test Workshop* - Ilia Polian, Bernd Becker
**Optimal Bandwidth Allocation in Concurrent SoC Test Under Pin Number Constraints**

2002*Workshop on RTL and High Level Testing*, Seiten: 12 - 17 - J. Bradford, H. Delong, Ilia Polian, Bernd Becker
**Realistic Fault Simulation in an Industrial Setting**

2002*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, L. Linhard, G. Angst
**Recursive Bi-Partitioning of Netlists for Large Number of Partitions**

2002*Euromicro Conf.*, Seiten: 38 - 44 - Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker
**Sequential n-Detection Criteria: Keep It Simple!**

2002*IEEE Int'l Online Testing Workshop*, Seiten: 189 - 190 - J. Bradford, H. Delong, Ilia Polian, Bernd Becker
**Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting**

2002*European Test Workshop*, Seiten: 75 - 80 - Ilia Polian, Bernd Becker
**Stop & Go BIST**

2002*IEEE Int'l Online Testing Workshop*, Seiten: 147 - 151 - Klaus-Jürgen Englert, Rolf Drechsler, Bernd Becker
**Verification of HDLs using Symbolic Set Representation**

2002

## 2001

nach oben zur Jahresübersicht- Rolf Drechsler, J. Römmler
**Implementation and Visualization of a BDD Package in JAVA**

, 2001 - Marc Herbstritt
**zChaff: Modifications and Extensions**

, Nummer: 188, 2001 - Wolfgang Günther, Andreas Hett, Bernd Becker
**Application of Linearly Transformed BDDs in Sequential Verification**

2001*ASP Design Automation Conf.*, Seiten: 91 - 96 - Christoph Scholl, Bernd Becker
**Checking Equivalence for Partial Implementations**

2001 - Christoph Scholl, Bernd Becker
**Checking Equivalence for Partial Implementations**

2001*IEEE Design Automation Conference*, IEEE Computer Society, Seiten: 238 - 243 - Bernd Becker, Christoph Meinel, Masahiro Fujita, Fabio Somenzi
**Computer Aided Design and Test, BDDs versus SAT, Dagstuhl-Seminar-Report 297, 28.01.-02.02.01**

2001*Saarbrücken: Geschäftsstelle Schloss Dagstuhl* - Christoph Scholl, Marc Herbstritt, Bernd Becker
**Don't Care Minimization of *BMDs: Complexity and Algorithms**

2001 - Rolf Drechsler
**Educational Software for Computer Engineering: A Case Study of an Interactive BDD Tool**

2001*IEEE Computer Society Learning Technology Task Force*, Band: 3, Nummer: 3 - Ilia Polian, Wolfgang Günther, Bernd Becker
**Efficient Pattern-Based Verification of Connections to Intellectual Property Cores**

2001*IEEE Asian Test Symp.*, Seiten: 443 - 448 - Ilia Polian, Wolfgang Günther, Bernd Becker
**Efficient Pattern-Based Verification of Connections to Intellectual Property Cores**

2001 - Christoph Scholl, Marc Herbstritt, Bernd Becker
**Exploiting Don't Cares to Minimize *BMDs**

2001*IEEE Int'l Symp. on Circuits and Systems*, Band: 5, Seiten: 191 - 194 - Christoph Scholl
**Functional Decomposition with Application to FPGA Synthesis**

Kluwer Academic Publishers, 2001 - Bernd Becker, Rolf Drechsler, Thomas Eschbach, Wolfgang Günther
**GREEDY IIP: Partitioning Large Graphs by Greedy Iterative Improvement**

2001*Euromicro Conf.*, Seiten: 54 - 60 - Nicole Drechsler, Frank Schmiedle, Daniel Große, Rolf Drechsler
**Heuristic Learning based on Genetic Programming**

2001*EuroGP*, Springer Verlag, Band: 2038, Seiten: 1 - 10 - Wolfgang Günther, Rolf Drechsler
**Implementation of Read-k-times BDDs on top of standard BDD packages**

2001*Int'l Conf. on VLSI Design*, Seiten: 173 - 178 - Rolf Drechsler, Wolfgang Günther, L. Linhard, G. Angst
**Level Assignment for Displaying Combinational Logic**

2001*Euromicro Conf.*, Seite: 148 - Ilia Polian, Bernd Becker
**Multiple Scan Chain Design for Two-Pattern Testing**

2001*VLSI Test Symp.*, Seiten: 88 - 93 - Ilia Polian, Bernd Becker
**Multiple Scan Chain Design for Two-Pattern Testing**

2001*Latin-American Test Workshop*, Seiten: 156 - 161 - Ilia Polian, Bernd Becker
**Multiple Scan Chain Design for Two-Pattern Testing**

2001*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Wolfgang Günther, Rolf Drechsler
**Performance Driven Optimization for MUX based FPGAs**

2001*Int'l Conf. on VLSI Design*, Seiten: 311 - 316 - Frank Schmiedle, Nicole Drechsler, Daniel Große, Rolf Drechsler
**Priorities in Multi-Objective Optimization for Genetic Programming**

2001*Conf. on Genetic and Evolutionary Computation*, Seiten: 129 - 136 - Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
**Selection of Efficient Re-Ordering Heuristics for MDD Construction**

2001*Int'l Symp. on Multi-Valued Logic*, Seiten: 299 - 304 - M. Thornton, Rolf Drechsler, D. M. Miller
**Spectral Techniques in VLSI CAD**

Kluwer Academic Publisher, 2001 - Andreas Hett, Bernd Becker
**Supervised Dynamic Reordering in Model Checking**

2001 - Christoph Scholl, Bernd Becker, A. Brogle
**The Multiple Variable Order Problem for Binary Decision Diagrams: Theory and Practical Application**

2001*ASP Design Automation Conf.*, Seiten: 85 - 90 - Frank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker
**Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics**

2001*Int'l Conf. on Computational Intelligence*, Band: 2206, Seiten: 479 - 491 - Rolf Drechsler, Wolfgang Günther, Fabio Somenzi
**Using Lower Bounds during Dynamic BDD Minimization**

2001*IEEE Trans. on CAD*, Band: 20, Nummer: 1, Seiten: 51 - 57 - P. Johannsen, Rolf Drechsler
**Utilizing High-Level Information for Formal Hardware Verification (Invited Talk)**

2001*Advanced Computer Systems*, Seiten: 419 - 431 - Frank Schmiedle, A. Markert, Bernd Becker
**XMaDRE: A Routing Environment with Visualization based on Ray-Tracing**

2001*Conf. on Design, Automation and Test in Europe*

## 2000

nach oben zur Jahresübersicht- Christoph Scholl, Bernd Becker
**Checking Equivalence for Partial Implementations**

, Nummer: 145, 2000 - Christoph Scholl, Marc Herbstritt, Bernd Becker
**Exploiting Don't Cares to Minimize *BMDs**

, Nummer: 141, 2000 - M. A. Thornton, Rolf Drechsler, Wolfgang Günther
**A Method for Approximate Equivalence Checking**

2000*Int'l Symp. on Multi-Valued Logic*, Seiten: 447 - 452 - Piet Engelke, Bernd Becker, Martin Keim
**A Parameterizable Fault Simulator for Bridging Faults**

2000*European Test Workshop*, Seiten: 63 - 68 - Martin Keim, Piet Engelke, Bernd Becker
**A Parameterizable Fault Simulator for Bridging Faults**

2000*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Wolfgang Günther, Rolf Drechsler
**ACTion: Combining Logic Synthesis and Technology Mapping for MUX based FPGAs**

2000*Journal of Systems Architecture*, Band: 46, Nummer: 14, Seiten: 1321 - 1334 - Wolfgang Günther, Rolf Drechsler
**ACTion: Combining Logic Synthesis and Technology Mapping for MUX based FPGAs**

2000*Int'l Workshop on Logic Synth.* - Wolfgang Günther, Rolf Drechsler
**ACTion: Combining Technology Mapping and Logic Synthesis for MUX based FPGAs**

2000*Euromicro Conf.*, Seiten: 130 - 137 - Rolf Drechsler, Nicole Drechsler, Elke Mackensen, Tobias Schubert, Bernd Becker
**Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System**

2000*Euromicro Conf.*, Seiten: 1:425 - 431 - Andreas Hett, Christoph Scholl, Bernd Becker
**Distance Driven Finite State Machine Traversal**

2000*IEEE Design Automation Conference*, Seiten: 39 - 42 - Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
**Dynamic Re-Encoding During MDD Minimization**

2000*Int'l Symp. on Multi-Valued Logic*, Seiten: 239 - 244 - Wolfgang Günther, Rolf Drechsler, S. Höreth
**Efficient Dynamic Minimization of Word-Level DDs based on Lower Bound Computation**

2000*Int'l Workshop on Logic Synth.* - Wolfgang Günther, Rolf Drechsler, S. Höreth
**Efficient Dynamic Minimization of Word-Level DDs based on Lower Bound Computation**

2000*Int'l Conf. on Computer Design*, Seiten: 383 - 388 - Rolf Drechsler, Wolfgang Günther
**Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints**

2000*Conf. on Genetic and Evolutionary Computation*, Seiten: 513 - 518 - Frank Schmiedle, D. Unruh, Bernd Becker
**Exact Switchbox Routing with Search Space Reduction**

2000*Int'l Symp. on Physical Design*, Seiten: 26 - 32 - Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
**Fast Exact Minimization of BDDs**

2000*IEEE Trans. on CAD*, Band: 19, Nummer: 3, Seiten: 384 - 389 - Rolf Drechsler
**Formal Verification of Circuits**

Kluwer Academic Publishers, 2000 - Wolfgang Günther, Rolf Drechsler
**Improving EAs for Sequencing Problems**

2000*Conf. on Genetic and Evolutionary Computation*, Seiten: 175 - 180 - Dragan Janković, Wolfgang Günther, Rolf Drechsler
**Lower Bound Sifting for MDDs**

2000*Int'l Symp. on Multi-Valued Logic*, Seiten: 193 - 198 - Wolfgang Günther
**Minimization of Free BDDs using Evolutionary Techniques**

2000*Int'l Workshop on Logic Synth.*, Seiten: 167 - 172 - Wolfgang Günther, Rolf Drechsler
**On the Computational Power of Linearly Transformed BDDs**

2000*Information Processing Letters*, Band: 75, Nummer: 3, Seiten: 119 - 125 - Rolf Drechsler, Wolfgang Günther
**Optimization of Sequential Verification by History-Based Dynamic Minimization of BDDs**

2000*IEEE Int'l Symp. on Circuits and Systems*, Seiten: IV:737 - IV:740 - Tobias Schubert, Elke Mackensen, Nicole Drechsler, Rolf Drechsler, Bernd Becker
**Specialized Hardware for Implementation of Evolutionary Algorithms**

2000*Int'l Workshop on Boolean Problems*, Seiten: 175 - 182 - Tobias Schubert, Elke Mackensen, Nicole Drechsler, Rolf Drechsler, Bernd Becker
**Specialized Hardware for Implementation of Evolutionary Algorithms**

2000*Conf. on Genetic and Evolutionary Computation*, Seite: 369 - Wolfgang Günther
**Speeding up Dynamic Minimization of Linearly Transformed BDDs**

, Nummer: 144, 2000 - Andreas Hett, Christoph Scholl, Bernd Becker
**State Traversal guided by Hamming Distance Profiles**

2000 - Rolf Drechsler, Wolfgang Günther, Bernd Becker
**Testability of Circuits Derived from Lattice Diagrams**

2000*Euromicro Conf.*, Seiten: 188 - 192 - Rolf Drechsler, Wolfgang Günther, Bernd Becker
**Testability of Circuits Derived from Lattice Diagrams**

2000*Latin-American Test Workshop* - Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
**Verification of Designs Containing Black Boxes**

2000 - Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker
**Verification of Designs Containing Black Boxes**

2000*Euromicro Conf.*, Seiten: 100 - 105 - Wolfgang Günther, R. Schönfeld, Bernd Becker, Paul Molitor
**k-Layer Straightline Crossing Minimization by Speeding up Sifting**

2000*Graph Drawing Conf.*, Springer Verlag, Band: 1984, Seiten: 253 - 258

## 1999

nach oben zur Jahresübersicht- Christoph Scholl, Bernd Becker, A. Brogle
**Solving the Multiple Variable Order Problem for Binary Decision Diagrams by Use of Dynamic Reordering Techniques**

, Nummer: 130, 1999 - Rolf Drechsler, Marc Herbstritt, Bernd Becker
**Grouping Heuristics for Word-level Decision Diagrams**

1999*IEEE Int'l Symp. on Circuits and Systems*, Seiten: 411 - 415 - Rolf Drechsler, Bernd Becker
**Probabilistic IP Verification**

1999*Int'l Workshop on Testing Embedded Core-based System-Chips* - Nicole Drechsler, Rolf Drechsler, Bernd Becker
**A New Model for Multi-Objective Optimization in Evolutionary Algorithms**

1999*Int'l Conf. on Computational Intelligence*, Springer Verlag, Band: 1625, Seiten: 108 - 117 - Martin Keim, Ilia Polian, Harry Hengster, Bernd Becker
**A Scalable BIST Architecture for Delay Faults**

1999*European Test Workshop*, Seiten: 98 - 103 - Andreas Hett, Christoph Scholl, Bernd Becker
**A.MORE - A Multi-Operand BDD Package**

University of Freiburg, 1999 - Christoph Scholl, D. Möller, Paul Molitor, Rolf Drechsler
**BDD Minimization Using Symmetries**

1999*IEEE Trans. on CAD*, Band: 18, Nummer: 2, Seiten: 81 - 100 - Martin Keim, Nicole Drechsler, Bernd Becker
**Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits**

1999*ASP Design Automation Conf.*, Seiten: 315 - 318 - Bernd Becker, Christoph Meinel, Shin-Ichi Minato, Fabio Somenzi
**Computer Aided Design and Test, Decision Diagrams - Concepts and Applications, (99041), Dagstuhl-Seminar-Report 229, 24.01.-29.1.1999**

1999*Saarbrücken: Geschäftsstelle Schloss Dagstuhl* - Wolfgang Günther, Rolf Drechsler
**Creating Hard Problem Instances in Logic Synthesis using Exact Minimization**

1999*IEEE Int'l Symp. on Circuits and Systems*, Seiten: VI:436 - VI:439 - Paul Molitor, Christoph Scholl
**Datenstrukturen und effiziente Algorithmen fuer die Logiksynthese kombinatorischer Schaltungen**

B.G. Teubner, 1999 - Wolfgang Günther, Rolf Drechsler
**Efficient Manipulation Algorithms for Linearly Transformed BDDs**

1999*Int'l Conf. on CAD*, Seiten: 50 - 53 - Nicole Drechsler, Rolf Drechsler
**Exploiting Don't Cares During Data Sequencing using Genetic Algorithms**

1999*ASP Design Automation Conf.*, Seiten: 303 - 306 - S. Höreth, Rolf Drechsler
**Formal Verification of Word-Level Specifications**

1999*Conf. on Design, Automation and Test in Europe*, Seiten: 52 - 58 - Rolf Drechsler, Marc Herbstritt, Bernd Becker
**Grouping Heuristics for Word-level Decision Diagrams**

1999 - Rolf Drechsler, Wolfgang Günther
**History-based Dynamic Minimization during BDD Construction**

1999*IFIP Int'l Conf. on VLSI*, Seiten: 334 - 345 - Bernd Becker, Martin Keim, R. Krieger
**Hybrid Fault Simulation for Synchronous Sequential Circuit**

1999*Jour. Electronic Testing*, Band: 3, Seiten: 219 - 238 - Andreas Hett
**MORE good BDD Ideas**

1999*Dagstuhl Seminar on Computer Aided Design and Test, Decision Diagrams: Concepts and Applications* - Wolfgang Günther, Rolf Drechsler
**Minimization of BDDs using Linear Transformations based on Evolutionary Techniques**

1999*IEEE Int'l Symp. on Circuits and Systems*, Seiten: I:387 - I:390 - Wolfgang Günther, Rolf Drechsler
**Minimization of Free BDDs**

1999*ASP Design Automation Conf.*, Seiten: 323 - 326 - Christoph Scholl, Bernd Becker
**On the Generation of Multiplexer Circuits for Pass Transistor Logic**

1999*Int'l Workshop on Logic Synth.* - Y. Ye, K. Roy, Rolf Drechsler
**Power Consumption in XOR-Based Circuits**

1999*ASP Design Automation Conf.*, Seiten: 299 - 302 - Christoph Scholl, Bernd Becker, A. Brogle
**Solving the Multiple Variable Order Problem for Binary Decision Diagram by Use of Dynamic Reordering Techniques**

1999*Int'l Workshop on Logic Synth.* - Christoph Scholl, Bernd Becker, A. Brogle
**Solving the Multiple Variable Order Problem for Binary Decision Diagram by Use of Dynamic Reordering Techniques**

, Nummer: 130, 1999 - Harry Hengster, Bernd Becker
**Synthesis of Circuits Derived from Decision Diagrams - Combining Small Delay and Testability -**

1999*Int'l Symp. on Defect and Fault Tolerance*, Seiten: 268 - 275 - Per Lindgren, Rolf Drechsler, Bernd Becker
**Synthesis of Pseudo Kronecker Lattice Diagrams**

1999*Int'l Conf. on Computer Design*, Seiten: 307 - 310 - Rolf Drechsler, Wolfgang Günther
**Using Lower Bounds during Dynamic BDD Minimization**

1999*IEEE Design Automation Conference*, Seiten: 29 - 32 - Rolf Drechsler, Nicole Drechsler
**VLSI CAD and the Integration of Evolutionary Techniques**

CRC Press International Series on Computational Intelligence, 1999

## 1998

nach oben zur Jahresübersicht- Martin Keim, Nicole Göckel, Rolf Drechsler, Bernd Becker
**Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits**

, Nummer: 105/98, 1998 - Wolfgang Günther, Rolf Drechsler
**BDD Minimization by Linear Transformations**

1998*Advanced Computer Systems*, Seiten: 525 - 532 - Rolf Drechsler, Bernd Becker
**Binary Decision Diagrams - Theory and Implementation**

Kluwer Academic Publishers, 1998 - Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
**Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits**

1998*European Test Workshop*, Seiten: 141 - 142 - S. Höreth, Rolf Drechsler
**Dynamic Minimization of Word-Level Decision Diagrams**

1998*Conf. on Design, Automation and Test in Europe*, Seiten: 612 - 617 - G. Lee, Rolf Drechsler
**ETDD-based Generation of Complex Terms for Incompletely Specified Boolean Functions**

1998*ASP Design Automation Conf.*, Seiten: 75 - 80 - Rolf Drechsler
**Evolutionary Algorithms for VLSI CAD**

Kluwer Academic Publisher, 1998 - Rolf Drechsler, Wolfgang Günther
**Exact Circuit Synthesis**

1998*Int'l Workshop on Logic Synth.*, Seiten: 177 - 184 - Rolf Drechsler, Wolfgang Günther
**Exact Circuit Synthesis**

1998*Advanced Computer Systems*, Seiten: 517 - 524 - Rolf Drechsler, Bernd Becker
**Graphenbasierte Funktionsdarstellung**

B.G. Teubner, 1998 - M. Miller, Rolf Drechsler
**Implementing a Multiple-Valued Decision Diagram Package**

1998*Int'l Symp. on Multi-Valued Logic*, Seiten: 52 - 57 - Wolfgang Günther, Rolf Drechsler
**Linear Transformations and Exact Minimization of BDDs**

1998*Great Lakes Symp. on VLSI*, Seiten: 325 - 330 - Christoph Scholl
**Multi-output Functional Decomposition with Exploitation of Don't Cares**

1998*Conf. on Design, Automation and Test in Europe*, Seiten: 743 - 748 - Martin Keim, Bernd Becker
**Nearly Exact Signal Probabilities for Synchronous Sequential Circuits - An Experimental Analysis**

, Nummer: 106/98, 1998 - M. Thornton, Rolf Drechsler
**Output Probability Using AND/OR Graphs**

1998*Research Report, University of Arkansas* - M. Thornton, Rolf Drechsler
**Spectral Methods for Digital Logic Verification**

1998*Research Report, University of Arkansas* - Harry Hengster, Bernd Becker
**Synthesis of Fully Testable High Speed Circuits Derived from Decision Diagrams**

1998*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Harry Hengster, Bernd Becker
**Synthesis of Fully Testable High Speed Circuits Derived from Decision Diagrams**

1998*Int'l Workshop on Logic Synth.*, Seiten: 341 - 345 - Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
**Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm**

1998*Int'l Symp. on Multi-Valued Logic*, Seiten: 215 - 220 - Martin Keim, Nicole Göckel, Rolf Drechsler, Bernd Becker
**Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm**

1998*Int'l Symp. on Multi-Valued Logic* - Rolf Drechsler, Martin Sauerhoff, Detlef Sieling
**The Complexity of the Inclusion Operation on OFDDs**

1998*IEEE Trans. on CAD*, Band: 17, Nummer: 5, Seiten: 457 - 459 - Rolf Drechsler
**Verifying Integrity of Decision Diagrams**

1998*SAFECOMP*, Springer Verlag, Band: 1516, Seiten: 380 - 389 - Christoph Scholl, Bernd Becker, T. M. Weis
**Word-Level Decision Diagrams, WLCDs and Division**

1998*Int'l Conf. on CAD*, Seiten: 672 - 677

## 1997

nach oben zur Jahresübersicht- Rolf Drechsler, Nicole Göckel
**A Genetic Algorithm for Data Sequencing**

1997*Electronic Letters*, Band: 33, Nummer: 10, Seiten: 843 - 845 - Nicole Göckel, Martin Keim, Rolf Drechsler, Bernd Becker
**A Genetic Algorithm for Sequential Circuit Test Generation based on Symbolic Fault Simulation**

1997*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Nicole Göckel, Martin Keim, Rolf Drechsler, Bernd Becker
**A Genetic Algorithm for Sequential Circuit Test Generation based on Symbolic Fault Simulation**

1997*European Test Workshop* - Nicole Göckel, Rolf Drechsler, Bernd Becker
**A Multi-Layer Detailed Routing Approach based on Evolutionary Algorithms**

1997*Int'l Conf. on Evolutionary Computation*, Seiten: 557 - 562 - Nicole Göckel, Rolf Drechsler
**An Evolutionary Algorithm for Minimizing BDDs of Incompletely Specified Functions**

1997*Advanced Computer Systems*, Seiten: 224 - 231 - Christoph Scholl, D. Möller, Paul Molitor, Rolf Drechsler
**BDD Minimization Using Symmetries**

, 1997 - Rolf Drechsler, Nicole Göckel, Elke Mackensen, Bernd Becker
**BEA: Specialized Hardware for Implementation of Evolutionary Algorithms**

1997*Genetic Programming Conf.*, Seite: 491 - S. Höreth, Rolf Drechsler
**Compilation of Fast Manipulation Algorithms for K*BMDs**

1997*IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design*, Seiten: 187 - 196 - Bernd Becker, Randy Bryant, Masahiro Fujita, Christoph Meinel
**Computer Aided Design and Test, Decision Diagrams - Concepts and Applications, (9705), Dagstuhl-Seminar-Report 166, 27.01.-31.1.1997**

1997*Saarbrücken: Geschäftsstelle Schloss Dagstuhl* - Bernd Becker, Rolf Drechsler
**Decision Diagrams in Synthesis - Algorithms, Applications and Extensions -**

1997*Int'l Conf. on VLSI Design*, Seiten: 46 - 50 - Rolf Drechsler, A. Zuzek
**Efficient Functional Diagnosis for Synchronous Sequential Circuits Based on AND/OR Graphs**

1997*Int'l Symp. on IC Technologies, Systems and Applications*, Seiten: 312 - 315 - Rolf Drechsler
**Evolutionary Algorithms for Computer Aided Design of Integrated Circuits**

1997*Int'l Symp. on IC Technologies, Systems and Applications*, Seiten: 302 - 311 - S. Höreth, Rolf Drechsler
**Fast Construction of Kronecker Decision Diagrams from Library Based Circuits**

1997*SASIMI*, Seiten: 39 - 44 - Rolf Drechsler, Nicole Göckel, Wolfgang Günther
**Fast Exact Minimization of BDDs**

, 1997 - Andreas Hett, Rolf Drechsler, Bernd Becker
**Fast and Efficient Construction of BDDs by reordering based Synthesis**

1997*European Design and Test Conf.*, Seiten: 168 - 175 - Rolf Drechsler, Martin Keim, Bernd Becker
**Fault Simulation in Sequential Multi-Valued Logic Networks**

1997*Int'l Symp. on Multi-Valued Logic*, Seiten: 145 - 150 - Christoph Scholl
**Functional Decomposition with Integrated Test Generation**

1997*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Christoph Scholl, Rolf Drechsler, Bernd Becker
**Functional Simulation using Binary Decision Diagrams**

1997*GI/ITG/GME Workshop “Methoden des Entwurfs und der Verifikation digitaler Systeme”* - Christoph Scholl, Rolf Drechsler, Bernd Becker
**Functional Simulation using Binary Decision Diagrams**

1997*Int'l Workshop on Logic Synth.* - Rolf Drechsler, Bernd Becker
**Graphenbasierte Funktionsdarstellung**

B.G. Teubner, 1997 - Nicole Göckel, Rolf Drechsler
**Influencing Parameters of Evolutionary Algorithms for Sequencing Problems**

1997*Int'l Conf. on Evolutionary Computation*, Seiten: 575 - 580 - Nicole Göckel, Rolf Drechsler, Bernd Becker
**Learning Heuristics for OKFDD Minimization by Evolutionary Algorithms**

1997*ASP Design Automation Conf.*, Seiten: 469 - 472 - Rolf Drechsler, Nicole Göckel
**Minimization of BDDs by Evolutionary Algorithms**

1997*Int'l Workshop on Logic Synth.* - Christoph Scholl
**Multi-output Functional Decomposition with Exploitation of Don't Cares**

1997*Int'l Workshop on Logic Synth.* - C. Ökmen, Martin Keim, R. Krieger, Bernd Becker
**On Optimizing BIST Architecture by Using OBDD-based Approaches and Genetic Algorithms**

1997*VLSI Test Symp.*, Seiten: 426 - 431 - Martin Keim, M. Martin, Bernd Becker, Rolf Drechsler, Paul Molitor
**Polynomial Formal Verification of Multipliers**

1997*VLSI Test Symp.*, Seiten: 150 - 155 - Rolf Drechsler
**Pseudo Kronecker Expressions for Symmetric Functions**

1997*Int'l Conf. on VLSI Design*, Seiten: 511 - 513 - Andreas Hett, Rolf Drechsler, Bernd Becker
**Reordering Based Synthesis**

1997*iwrm* - Rolf Drechsler
**Secure Implementation of Decision Diagrams**

1997*Int'l Workshop on Logic Synth.* - Rolf Drechsler, R. S. Stankovic, T. Sasao
**Spectral Transforms and Word-Level Decision Diagrams**

1997*IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design* - Rolf Drechsler, R. S. Stankovic, T. Sasao
**Spectral Transforms and Word-Level Decision Diagrams**

1997*SASIMI*, Seiten: 33 - 38 - Harry Hengster, Bernd Becker
**Synthesis of Fully Testable High Speed Circuits Derived from Decision Diagrams**

, 1997 - Rolf Drechsler, Harry Hengster, H. Schäfer, J. Hartmann, Bernd Becker
**Testability of 2-Level AND/EXOR Expressions**

1997*European Design and Test Conf.*, Seiten: 548 - 553

## 1996

nach oben zur Jahresübersicht- Rolf Drechsler, Nicole Göckel
**A Genetic Algorithm for Data Sequencing**

1996*Online Workshop on Evolutionary Computation* - Rolf Drechsler, Bernd Becker, Nicole Göckel
**A Genetic Algorithm for the Construction of Small and Highly Testable OKFDD Circuits**

1996*Genetic Programming Conf.*, Seiten: 473 - 478 - Nicole Göckel, G. Pudelko, Rolf Drechsler, Bernd Becker
**A Hybrid Genetic Algorithm for the Channel Routing Problem**

1996*IEEE Int'l Symp. on Circuits and Systems*, Seiten: IV:675 - IV:678 - Rolf Drechsler, Andreas Hett, Bernd Becker
**A Note on Symbolic Simulation using Desicion Diagrams**

1996*ulsi* - Harry Hengster, Rolf Drechsler, S. Eckrich, T. Pfeiffer, Bernd Becker
**AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth**

1996*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Harry Hengster, Rolf Drechsler, S. Eckrich, T. Pfeiffer, Bernd Becker
**AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth**

1996*IEEE Asian Test Symp.*, Seiten: 148 - 154 - Rolf Drechsler, A. Zuzek
**Efficient Functional Diagnosis for Synchronous Sequential Circuits based on AND/OR Graphs**

, 1996 - Bernd Becker, Rolf Drechsler
**Exact Minimization of Kronecker Expressions for Symmetric Functions**

1996*IEEE Int'l Symp. on Circuits and Systems*, Seiten: IV:388 - IV:391 - Rolf Drechsler, H. Esbensen, Bernd Becker
**Genetic Algorithms in Computer Aided Design of Integrated Circuits**

1996*Online Workshop on Evolutionary Computation* - Rolf Drechsler, Nicole Göckel, Bernd Becker
**Learning Heuristics for OBDD Minimization by Evolutionary Algorithms**

1996*Parallel Problem Solving from Nature*, Springer Verlag, Band: 1141, Seiten: 730 - 739 - Harry Hengster, U. Sparmann, Bernd Becker, Sudhakar M. Reddy
**Local Transformations and Robust Dependent Path Delay Faults**

1996*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Harry Hengster, U. Sparmann, Bernd Becker, Sudhakar M. Reddy
**Local Transformations and Robust Dependent Path Delay Faults**

1996*European Test Workshop* - Harry Hengster, U. Sparmann, Bernd Becker, Sudhakar M. Reddy
**Local Transformations and Robust Dependent Path Delay Faults**

1996*Int'l Test Conf.* - Andreas Hett, Rolf Drechsler, Bernd Becker
**MORE Optimization Techniques.**

, 1996 - Rolf Drechsler, Bernd Becker
**OKFDDs - Algorithms, Applications and Extensions**

Kluwer Academic Publisher, Seiten: 163 - 190, 1996 - Bernd Becker, Rolf Drechsler, Reinhard Enders
**On the Computational Power of Bit-Level and Word-Level Decision Diagrams**

1996*GI/ITG/GME Workshop “Methoden des Entwurfs und der Verifikation digitaler Systeme”* - Rolf Drechsler
**Pseudo Kronecker Expressions for Symmetric Functions**

, 1996 - Rolf Drechsler, Harry Hengster, H. Schäfer, Bernd Becker
**Testability of AND/EXOR Expressions**

1996*European Test Workshop* - Andreas Hett, Rolf Drechsler, Bernd Becker
**The DD Package PUMA - An Online Documentation**

https://ira.informatik.uni-freiburg.de/software/puma/, 1996 - Rolf Drechsler
**Verification of Multi-Valued Logic Networks**

1996*Int'l Symp. on Multi-Valued Logic*, Seiten: 10 - 15

## 1995

nach oben zur Jahresübersicht- Rolf Drechsler, Bernd Becker, Nicole Göckel
**A Genetic Algorithm for 2-Level AND/EXOR Minimization**

1995*SASIMI*, Seiten: 49 - 56 - Rolf Drechsler, Bernd Becker, Nicole Göckel
**A Genetic Algorithm for Variable Ordering of OBDDs**

1995*Int'l Workshop on Logic Synth.*, Seiten: 5c:5.55 - 5.64 - Rolf Drechsler, Bernd Becker, Nicole Göckel
**A Genetic Algorithm for Variable Ordering of OBDDs**

, Nummer: 5/95, 1995 - Harry Hengster, Rolf Drechsler, Bernd Becker
**AND/OR/EXOR based Synthesis of KFDD-Circuits with Small Depth**

1995*Reed-Muller Colloquium UK* - Bernd Becker, Randal Bryant, Olivier Coudert, Christoph Meinel
**Computer Aided Design and Test, Dagstuhl-Seminar-Report 105 (9507), 13.2.1995 - 17.2.1995**

1995*Saarbrücken: Geschäftsstelle Schloss Dagstuhl* - Rolf Drechsler, Bernd Becker, S. Ruppertz
**Dynamic Minimization of K*BMDs**

, 1995 - Rolf Drechsler, Bernd Becker
**Dynamic Minimization of OKFDDs**

, Nummer: 5/95, 1995 - Bernd Becker, Rolf Drechsler
**Exact Minimization of Kronecker Expressions for Symmetric Functions**

1995*IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design*, Seiten: 240 - 245 - R. Krieger, Bernd Becker, R. Sinković
**Necessary Assignments for an Accelerated OBDD-based Computation of Exact Fault Detection Probabilities**

1995*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - R. Krieger, Bernd Becker, C. Ökmen
**OBDD-based Optimization of Input probabilities for weighted random test**

1995*Int'l Symp. on Defect and Fault Tolerance*, Seiten: 120 - 129 - Bernd Becker, Rolf Drechsler, M. Theobald
**OKFDDs versus OBDDs and OFDDs**

1995*ICALP*, Springer Verlag, Band: 944, Seiten: 475 - 486 - Bernd Becker, Rolf Drechsler, Reinhard Enders
**On the Computational Power of Bit-Level and Word-Level Decision Diagrams**

, 1995 - Bernd Becker, Rolf Drechsler, R. Werchner
**On the Relation Between BDDs and FDDs**

1995*Information and Computation*, Band: 123(2), Seiten: 185 - 197 - Rolf Drechsler
**Ordered Kronecker Functional Decision Diagrams und ihre Anwendungen**

Modell Verlag, Ph.D. thesis at J.W. Goethe-Universität, 1995 - Rolf Drechsler, Bernd Becker
**PUMA: An OKFDD-Package and its Implementation**

1995*European Design and Test Conf.* - R. Krieger, Bernd Becker, Martin Keim
**Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy**

1995*IEEE Design Automation Conference*, Seiten: 339 - 344 - Bernd Becker, Rolf Drechsler
**Synthesis for Testability: Circuits Derived from Ordered Kronecker Functional Decision Diagrams**

1995*European Design and Test Conf.*, Seite: 592

## 1994

nach oben zur Jahresübersicht- Rolf Drechsler
**BiTeS: A BDD based test pattern generator for strong robust path delay faults**

1994*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Rolf Drechsler
**BiTeS: A BDD based test pattern generator for strong robust path delay faults**

1994*European Design Automation Conf.*, Seiten: 322 - 327 - Rolf Drechsler, M. Theobald, Bernd Becker
**Fast FDD based Minimization of Generalized Reed-Muller Forms**

1994 Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen*Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen* - Rolf Drechsler, H. Esbensen, Bernd Becker
**Genetic Algorithms in Computer Aided Design of Integrated Circuits**

, Nummer: 17/94, 1994 - Bernd Becker, Rolf Drechsler, M. Theobald
**Minimization of 2-level AND/XOR Expressions using Ordered Kronecker Functional Decision Diagrams**

, Nummer: 3/94, 1994 - Rolf Drechsler, Bernd Becker, A. Jahnke
**On Variable Ordering and Decomposition Type Choice in OKFDDs**

1994*Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen* - Rolf Drechsler, Bernd Becker, A. Jahnke
**On Variable Ordering and Decomposition Type Choice in OKFDDs**

, Nummer: 11/94, 1994 - Bernd Becker, Rolf Drechsler, M. Theobald
**On Variable Ordering of Functional Decision Diagrams**

, Nummer: TR-94-006, 1994 - Bernd Becker, Rolf Drechsler, M. Theobald
**On Variable Ordering of Ordered Functional Decision Diagrams**

1994*GI/GME/ITG-Fachtagung “Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme”*, Springer Verlag, Seiten: 62 - 71 - Rolf Drechsler, A. Sarabi, M. Theobald, Bernd Becker, M. A. Perkowski
**On the Computational Power of Ordered Kronecker Functional Decision Diagrams**

, Nummer: 4/94, 1994 - Rolf Drechsler, A. Sarabi, M. Theobald, Bernd Becker, M. A. Perkowski
**Ordered Kronecker Functional Decision Diagrams: An Efficient Tool for Synthesis and Verification**

1994*GI/ITG Workshop “Anwendung formaler Methoden im Systementwurf”* - D. Möller, Paul Molitor, Rolf Drechsler
**Symmetry based Variable Ordering for ROBDDs**

1994*IFIP Workshop on Logic and Architecture Synthesis, Grenoble*, Seiten: 47 - 53 - Bernd Becker, Rolf Drechsler
**Synthesis for Testability: Circuits Derived from Ordered Kronecker Functional Decision Diagrams**

1994*Int'l Test Synthesis Workshop* - Bernd Becker, Rolf Drechsler
**Synthesis for Testability: Circuits Derived from Ordered Kronecker Functional Decision Diagrams**

, Nummer: 14/94, 1994 - Harry Hengster, Rolf Drechsler, Bernd Becker
**Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model**

1994*Int'l Conf. on VLSI Design*, Seiten: 123 - 126 - Bernd Becker, Rolf Drechsler
**Testability of Circuits Derived from Functional Decision Diagrams**

1994*European Design and Test Conf.*, Seite: 667

## 1993

nach oben zur Jahresübersicht- Bernd Becker, Rolf Drechsler, Harry Hengster, R. Krieger, R. Sinković
**Binary Decision Diagrams and Testing**

1993*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Bernd Becker, Randal Bryant, Christoph Meinel
**Computer Aided Design and Test: 15.2.1993-19.2.1993 (9307), Dagstuhl Seminar Report 56**

1993*Saarbrücken: Geschäftsstelle Schloss Dagstuhl* - Rolf Drechsler, A. Sarabi, M. Theobald, Bernd Becker, M. A. Perkowski
**Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams**

, Nummer: 14/93, 1993 - Rolf Drechsler, M. Theobald, Bernd Becker
**Fast FDD based Minimization of Generalized Reed-Muller Forms**

, Nummer: 15/93, 1993 - Bernd Becker, Rolf Drechsler, Harry Hengster
**Local Circuit Transformations Preserving Robust Path-Delay-Fault Testability**

, Nummer: 1/93, 1993 - Bernd Becker, Rolf Drechsler, Paul Molitor
**On Generation of Area-Time Optimal Testable Adders**

1993*Technical Report 3/93* - Bernd Becker, Rolf Drechsler, M. Theobald
**On Variable Ordering of Functional Decision Diagrams**

, 1993 - Bernd Becker, Rolf Drechsler
**On the Computational Power of Functional Decision Diagrams**

1993 Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen*Workshop über Komplexitätstheorie, Datenstrukturen und effiziente Algorithmen* - Bernd Becker, Rolf Drechsler, M. Theobald
**On the Implementation of a Package for Efficient Representation and Manipulation of Functional Decision Diagrams**

1993*IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design*, Seiten: 162 - 169 - Bernd Becker, Rolf Drechsler, R. Werchner
**On the Relation between BDDs and FDDs**

, Nummer: 12/93, 1993 - Bernd Becker, Rolf Drechsler, Christoph Meinel
**On the Testability of Circuits Derived from Binary Decision Diagrams**

, Nummer: 9/93, 1993 - Rolf Drechsler, Bernd Becker
**Rapid Prototyping of Fully Testable Multi-Level AND/EXOR Networks**

1993*IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design*, Seiten: 126 - 133 - Bernd Becker, Rolf Drechsler
**Testability of Circuits Derived from Functional Decision Diagrams**

, 1993 - Ralf Hahn, Bernd Becker, Harry Hengster
**The Fault Graph and its Application to Combinational Fault Simulation**

1993*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - R. Krieger, Bernd Becker, Harry Hengster
**lgc++: Ein Werkzeug zur Implementierung von Logiken als abstrakte Datentypen in C++**

, 1993 - R. Krieger, Ralf Hahn, Bernd Becker
**test_circ: Ein abstrakter Datentyp zur Repräsentation von hierarchischen Schaltkreisen**

, 1993

## 1992

nach oben zur Jahresübersicht- Rolf Drechsler, Bernd Becker, Paul Molitor
**A Performance Oriented Generator for Robust Path-Delay-Fault Testable Adders**

1992*GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”* - Bernd Becker, Rolf Drechsler, Paul Molitor
**On the Implementation of an Efficient Performance Driven Generator for Conditional-Sum-Adders.**

1992*Technical Report 2/93* - Rolf Drechsler, Bernd Becker
**Rapid Prototyping of Robust Path-Delay-Fault Testable Circuits Derived from Binary Decision Diagrams**

, Nummer: TR-17/92, SFB 124, 1992

## 1991

nach oben zur Jahresübersicht- Bernd Becker, Christoph Meinel
**Entwerfen, Prüfen, Testen: 18.2.1991-22.2.1991 (9108), Dagstuhl-Seminar-Report 6**

1991*Saarbrücken: Geschäftsstelle Schloss Dagstuhl*

## 1988

nach oben zur Jahresübersicht- Bernd Becker, U. Sparmann
**A Uniform Test Approach for RCC-Adders**

1988*Aegean Workshop on Parallel Computation and VLSI Theory*, Springer Verlag, Band: 319, Seiten: 288 - 300

## 1987

nach oben zur Jahresübersicht- Bernd Becker
**An Easily Testable Optimal-Time VLSI-Multiplier**

1987*Acta Informatica*, Band: 24, Seiten: 363 - 380 - Bernd Becker, G. Hotz, R. Kolla, Paul Molitor, H. G. Osthof
**CADIC - Ein System zum hierarchischen Entwurf integrierter Schaltungen**

1987*E.I.S.-Workshop*, Seiten: 235 - 245 - Bernd Becker, H. G. Osthof
**Layouts with Wires of Balanced Length**

1987*Information and Computation*, Band: 73(1), Seiten: 45 - 58

## 1986

nach oben zur Jahresübersicht- Bernd Becker, G. Hotz, R. Kolla, Paul Molitor
**Ein logisch-topologischer Kalkül zur Konstruktion von integrierten Schaltkreisen**

1986*INFORMATIK Forschung und Entwicklung 1*, Seite: 38--47,72-

## 1983

nach oben zur Jahresübersicht- Bernd Becker
**On the Crossing-free, Rectangular Embedding of Weighted Graphs in the Plane**

1983*Theor. Comput. Sci., GI-Conf.*, Springer Verlag, Band: 145, Seiten: 61 - 72