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Betreff: D Flip Flop with OR gate delay

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Gesendet von Matthew Lewis am 24. Juni 2003 um 11:00 Uhr.

Hello,
during the tutorial a few groups used the D Flip Flop with an OR gate delay for their flop flop. This design will not work in an FPGA as the compiler will replace the "OR Gate" delay chain with a "line" or "wire" as they are logically the same. They are not the same with respect to delay but the compiler will not realize that.
So if you wish to make a flip flop from basic gates you will have to use a master-slave design.
Matt

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Re: D Flip Flop with OR gate delay chenfei 24.06.03 (0)

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Letzte Änderung: März 2003, Tobias Schubert

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Nachricht:	: Hello, : during the tutorial a few groups used the D Flip Flop with an OR gate delay for their flop flop. This design will not work in an FPGA as the compiler will replace the "OR Gate" delay chain with a "line" or "wire" as they are logically the same. They are not the same with respect to delay but the compiler will not realize that. : So if you wish to make a flip flop from basic gates you will have to use a master-slave design. : Matt