2008

 nach oben zur Jahresübersicht

• Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker
  On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
  2008 IEEE Trans. on CAD, Band: 27, Nummer: 2, Seiten: 327 - 338
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  Kurzfassung

  Test application at reduced power supply voltage (low-voltage testing) or reduced temperature (low-temperature testing) can improve the defect coverage of a test set, in particular of resistive short defects. Using a probabilistic model of these defects, we quantify the coverage impact of low-voltage and low-temperature testing for different voltages and temperatures. When considering the coverage increase, we differentiate between defects missed by the test set at nominal conditions and undetectable defects (flaws) detected at non-nominal conditions. In our analysis, the performance degradation of the device caused by lower power supply voltage is accounted for. Furthermore, we describe a situation in which defects detected by conventional testing are missed by low-voltage testing and quantify the resulting coverage loss. Experimental results suggest that test quality is improved even if no cost increase is allowed. If multiple test applications are acceptable, a combination of low-voltage and low-temperature turns out to provide the best coverage of both hard defects and flaws.

2007

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• Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
  Power Droop Testing
  2007 Test of Computers, Band: 24, Nummer: 3, Seiten: 276 - 284

2006

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• Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
  Power Droop Testing
  2006 Int'l Conf. on Computer Design, Seiten: 243 - 250
• Sandip Kundu, Ilia Polian
  An Improved Technique for Reducing False Alarms Due to Soft Errors
  2006 Int'l On-Line Test Symp., Seiten: 105 - 110
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  Kurzfassung

  A significant fraction of soft errors in modern microprocessors has been reported to never lead to a system failure. Any concurrent error detection scheme that raises alarm every time a soft error is detected will not be well heeded because most of these alarms are false and responding to them will affect system performance negatively. This paper improves state of the art in detecting and preventing false alarms. Existing techniques are enhanced by a methodology to handle soft errors on address bits. Furthermore, we demonstrate benefit of false alarm identification in implementing a roll-back recovery system by first calculating the optimum check pointing interval for a roll-back recovery system and then showing that the optimal number of check-points decrease by orders of magnitude when exclusion techniques are used even if the implementation of exclusion technique is not perfect.

2005

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• Sandip Kundu, Matthew Lewis, Ilia Polian, Bernd Becker
  A Soft Error Emulation System for Logic Circuits
  2005 GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Seiten: 10 - 14
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  Kurzfassung

  In nanometer technologies, soft errors in logic circuits are increasingly important. Since the failure in time (FIT) rates for these circuits are very low, millions of test vectors are required for a realistic analysis of soft errors. This exceeds the capabilities of software simulation tools. We propose an FPGA emulation architecture that can apply millions of vectors within seconds. Comprehensive soft error profiling was done for ISCAS 89 circuits. Soft errors were assigned to four different classes, and their latency and recovery time were obtained. This information is useful for understanding the vulnerability of the system to soft errors and hardening it against such errors.
• Sandip Kundu, Matthew Lewis, Ilia Polian, Bernd Becker
  A Soft Error Emulation System for Logic Circuits
  2005 Conf. on Design of Circuits and Integrated Systems, Seite: 137
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  Kurzfassung

  In nanometer technologies, soft errors in logic circuits are increasingly important. Since the failure in time (FIT) rates for these circuits are very low, millions of test vectors are required for a realistic analysis of soft errors. This exceeds the capabilities of software simulation tools. We propose an FPGA emulation architecture that can apply millions of vectors within seconds. Comprehensive soft error profiling was done for ISCAS 89 circuits. Soft errors were assigned to four different classes, and their latency and recovery time were obtained. This information is useful for understanding the vulnerability of the system to soft errors and hardening it against such errors.
• Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker
  On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
  2005 IEEE Asian Test Symp., Seiten: 266 - 269
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  Kurzfassung

  Resistive defects are gaining importance in very-deep-submicron technologies, but their detection conditions are not trivial. Test application can be performed under reduced temperature and/or voltage in order to improve detection of these defects. This is the first analytical study of resistive bridge defect coverage of CMOS ICs under low-temperature and mixed low-temperature, low-voltage conditions. We extend a resistive bridging fault model in order to account for temperature-induced changes in detection conditions. We account for changes in both the parameters of transistors involved in the bridge and the resistance of the short defect itself. Using a resistive bridging fault simulator, we determine fault coverage for low-temperature testing and compare it to the numbers obtained at nominal conditions. We also quantify the coverage of flaws,i.e. defects that are redundant at nominal conditions but could deteriorate and become early-life failures. Finally, we compare our results to the case of low-voltage testing and comment on combination of these two techniques.
• Ilia Polian, Sandip Kundu, Jean-Marc Galliere, Piet Engelke, Michel Renovell, Bernd Becker
  Resistive Bridge Fault Model Evolution From Conventional to Ultra Deep Submicron Technologies
  2005 VLSI Test Symp., Seiten: 343 - 348
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  Kurzfassung

  We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) and a technology-specific part. The first model is based on Shockley equations and is valid for conventional but not deep submicron CMOS. The second model is obtained by fitting SPICE data. The third resistive bridging fault model uses Berkeley Predictive Technology Model and BSIM4; it is valid for CMOS technologies with feature sizes of 90nm and below, accurately describing non-trivial electrical behavior in that technologies. Experimental results for ISCAS circuits show that the test patterns obtained for the Shockley model are still valid for the Fitted model, but lead to coverage loss under the Predictive model.
• Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker
  Transient Fault Characterization in Dynamic Noisy Environments
  2005 Int'l Test Conf., Seiten: 10 pp. - 1048